Inovance H3U Series - Page 201

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4
4 Instructions4.5.4 Data Rotation and Shift
SFTL: Bit shift left
◆
Overview
When driving conditions are met, the SFTL instruction shifts a combination of bit elements with a length
of K1 from head address D to the left by K2 bit places, to accommodate a combination of bit elements
with a length of K2 from head address S that ll the lower bits. The K2 higher bits that are moved out are
discarded. The original values in the bit element combination S remain unchanged.
SFTL S D n1 n2
Bit shift left Applicable model:
H3U
S
Bit element
head
address
Head address of shifted bit elements
16-bit instruction
(9 steps)
SFTL:
Continuous
execution
SFTLP: Pulse
execution
D
Incoming
bit head
address
Head address of incoming bit elements
n1
Incoming
bit count
Number of incoming bit elements
n2
Bit element
count
Number of shifted bit elements
◆
Operands
Operand
Bit Element Word Element
System·User System·User Bit Designation Indexed Address Constant
Real
Number
S X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
D X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
n1 X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
n2 X Y M T C S SM D R T C SD KnX KnY KnM KnS KnSM
V,Z
Modication K H E
Note: The elements in gray background are supported.
◆
Function
n1 bit variables from head address D are shifted n2 bit places to the left, to accommodate n2 bit variables
from head address S that ll the lower bits.
The instruction of the pulse execution type is generally used.
The variable types applicable to the operands of SFTR and SFTL are as follows: