Chapter 13:
Theory of Operations
Stereo Audio ADC
This block converts the analog audio to digital. The sample rate will be one of 32kHz,
44.1kHz, or 48kHz (user configurable), with a word length of 20 bits. All channels
share a common sample rate. The output of this block is serial I
2
S format. Since ADC
devices are clocked from the same sample clock, a four-wire interface, with two data
channels is used.
The sample clock is derived from the 27MHz system clock, using a PLL and dividers.
This clock is also used to drive the MCLK for the sample rate converters.
Digital Input
The digital input connector is a 25-pin D-sub-miniature connector. An external
breakout cable provides the physical AES/EBU connectors. The digital input supports
both 110Ω and 75Ω formats, selectable through menu options. Bypass relays allow
the digital output to be connected to the digital input in the absence of power to the
unit.
The digital audio receiver accepts the AES/EBU data and converts it to the I
2
S format.
The digital input also accepts a data format. One of the AES/EBU receivers may be
designated as the data channel. In this mode, the SDI embedding function is not
available. The analog audio channels function normally. The primary use for this
mode is to allow Dolby AC3 or E streams to pass through the synchronizer with a
fixed delay.
SDI/DV Embedded Audio Input
The SDI and DV video formats may also carry embedded audio. The video processor
card extracts the embedded audio and sends it to the audio card via an I
2
S interface.
The SDI/DV multiplexing is done on the video card. The input data available will be
either two stereo-pair channels available from SDI, or one stereo-pair channel
available from DV. In the case of SDI, both stereo-pair channels share a common
sample clock. The SDI / DV sample clock is not necessarily synchronous to the
output system clock.
Multiplexor
The multiplexor selects which of the six stereo-pair streams is processed by each of
the two delay streams. The selection is controlled from the microprocessor. A
DigiPlex path allows the SDI/DV pairs to bypass the delay processor and go directly
to the analog or digital outputs. In addition, the unprocessed digital and analog inputs
may be routed to any of the outputs.
Sample Rate Converter
The sample rate converter block performs two functions. When the AES, SDI, or DV
data is received, it must be converted to a sample rate that is locked to the output
video clock. In addition, when Auto-Track is enabled, the sample rate converter
provides for the digital filtering of the audio when the audio delay is changed.
The sample rate converter output clock is derived from a second PLL. This PLL has
incremental increases or decreases in frequency to implement the incremental changes
in delay. The output of the sample rate converter block is two I
2
S format serial audio
streams.
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