Chapter 13:
Theory of Operations
For 20-bit audio data, bit locations 21 through 24 are set to '0'. The 'U' and 'C' bits
carry User data and Channel Status data, respectively. The 'Z' bit is a flag indicating
the start of a 192-bit block of user and channel status information. Note that the Z, U,
and C bits are reserved for future expansion and are not used within the audio sub-
system. The I2S bus has 32 bits within one time slot and 2 time slots. The frame sync
(or LRCK) is advanced by 1 bit compared to the data. Bits 0, 25, 26, 27, and 31 are
reserved.
Implementation
Analog Input Stage
The maximum input levels to the card are +24dBu. This translates into a voltage of
17.36Vp across the input terminals. The programmable gain control device (Crystal
CS3310, two required) has input levels that are 3.75Vp, single ended. If a differential
receiver with gain of -6dB is used (AD SSM2143 or BB INA137, two required), the
output voltage will be 17.36Vpp. Therefore, the input receiver section needs an
additional attenuation of 7.5/17.36 (0.4320). This attenuation is implemented using a
resister divider network.
The ADC (Crystal CS4222, two required) has a differential input of 2V
rms
(typical -
5.6Vpp). The output of the gain control device is 3.75Vp. Therefore, the section
between the gain control device and the ADC requires both a gain of 1.4/3.375
(0.415), and a single-ended to differential converter.
Analog Output Stage
The D/A converter (Crystal CS4222) has a differential voltage output of 5.6Vpp,
centred around 2.3Vdc. The D/A also has a programmable gain control, eliminating
the need for an external one. The output stage needs to remove the DC component,
and to pass through an anti-alias filter (3
rd
-order Butterworth low pass, 25kHz). The
filter is implemented with a gain to reduce the required gain in the output stage.
The output of the card should have levels of +24dBu. For balanced outputs, this
translates to voltage levels of 17.35Vpp per output. Due to the 50Ω output impedance
of commercially available differential drivers (Burr-Brown DRV135), there is
insufficient drive strength to achieve +24dBu into a 600 Ω termination with power
supply rails of +/-12V. Output impedance is reduced to 10 Ω and uses separate drivers
(Burr-Brown OPA4134, two required) for the positive and negative outputs to achieve
the +24dBu output rating. Taking into account the output impedance, the gain of the
output stage will be 17.35/5.6 (3.098).
The sample rate for the CODEC is determined by the data sent to the output stage.
This can be one of two sources: the SDI/DV recovered data, or the system sample
rate. The SDI/DV data is used in "Digi-Plex" mode only.
PLL Control
The Sample Rate PLL generates one of six system sample rates, based on the video
27MHz clock. This PLL is sent to the analog CODEC and the AES/EBU transmitters.
It is also used to read the data out of the delay buffer.
The Variable Rate PLL generates the same sample rate, but is allowed to change in
frequency to accommodate the variable video synchronisation delay. This PLL drives
the sample rate converters, and is used to write data into the delay buffers.
The dividers for both PLL (TI TLC2932) are generated inside the FPGA device. The
FPGA generates the sample clocks and bit clocks, as required.
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