Digital Input and Output
The digital AES transceiver (Crystal CS8420, two required) is used to convert the
AES stream to the I
2
S format The multiplexing between the 110Ω input and the 75Ω
input is done by an analog multiplex device (IDT QS4A205Q) prior to feeding the
AES receiver. A global parameter (AES Source) selects XLR or BNC (110Ω or 75Ω).
A built-in sample rate converter automatically converts the input data to the system
sample rate.
A digital AES transmitter is built into the AES receiver to convert the I
2
S stream to
AES format. The output of the transmitter drives both the 110Ω balanced and the 75Ω
unbalanced outputs. The levels for the 75Ω unbalanced output may be selected as
SPDIF or AES with a global programmable parameter (AES Elec. Levels).
For transcoding operations, the received digital input may be fed directly to the
analog output, and vice-versa.
Test Pattern Buffer
The test pattern buffer contains the test tone generator buffers and the auxiliary audio
stream buffers. It is implemented as a 256Kx16-word memory device. Each sample
uses 2 words of storage. With 8K samples utilized for each of the test tones, this
leaves 96K samples for the auxiliary audio stream. Since the auxiliary stream needs
both a Left and Right buffer, and since there needs to be double-buffer capability,
each buffer is 24K samples deep. This depth requires the microprocessor to fully fill
two auxiliary buffers every one-half second.
The FPGA controls addressing the test pattern buffer, and interfacing it to the
microprocessor.
Microprocessor Interface
The microprocessor interface is implemented in an FPGA and a CPLD. The CPLD is
responsible for those controllable signals which need to be available after power is
applied, but before the FPGA has been programmed. The FPGA is responsible for all
other programmable signals. The CPLD is responsible for providing the SPI-like
interface to those devices which require it.
An interface to the variable gain device is required. This is a SPI interface. A second
SPI interface is required to control the output level of the CODEC. A SPI or IIC
interface is required to communicate with the four sample rate converters. The relay
drivers need an interface, preferably parallel and non-volatile. The FPGA requires a
programming interface, SPI-like in nature. The previously mentioned interfaces are
implemented in a CPLD (XC9536XL).
The microprocessor interface consists of 16 data signals, 8 address signals, a RD
signal, a WR signal, and an IRQ signal. Additional signals include a "card installed"
signal that the audio card drives low when valid. The SPI/IIC interface is
implemented as a portal to the microprocessor I/F, with D15 being the SPI data line.
It is possible in some cases to implement reading of the SPI data under
microprocessor control. Reading the portal will yield the basic life-status of the card.
If A7 is high, the CPLD device is being addressed. Otherwise, the FPGA device is
being addressed. For the CPLD device, D7 through D0 always read the card status, as
defined in the table:
96
DPS-475/575 Service Manual
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