Toshiba TECRA 9100 Series - Page 67

2.4 System Board Troubleshooting 2 Troubleshooting Procedures
TECRA 9100 Maintenance Manual (960-347) 2-21
Table 2-3 Printer port LED boot mode status (2/6)
LED Status Test item Message
02h CMOS check and initialization Configuring cache memory
Enable L1 cache
CMOS access test
CMOS battery level check
CMOS checksum
CMOS data initialization (1)
Set IRT status
DRAM size storing in CMOS
03h Resume branch Resume branch check
SM-RAM checksum
SMI control flag clear
System BIOS RAM area checksum
System BIOS ROM to RAM copy
1FH Wake Up check
SMRAM base rewrite
20h PnP RAM checksum
PIT test and initialization
06h Grant SMI CPU check measure
Enabling SMI except for auto-off function
Set clock generator
Set CPU clock to high
Check model specific info
PIC register restore
KBC initialization
07h Resume process Resume process to resume main
Resume error process
System BIOS ROM/RAM copy AGP bridge initialization
04h SMRAM initialization SMRAM initialization
Wake Up check
SMRAM base rewrite and BIOS CPU state map store
Initializing SMRAM
05h Initializing a PIT and a CPU Initializing the channel 0 of a PIT
Initializing the channel 2 of a PIT
Testing the channel 1 of a PIT