Xilinx Virtex-4 Configuration User Guide

Virtex-4 FPGA Configuration User Guide www.xilinx.com 43
UG071 (v1.12) June 2, 2017
SelectMAP Configuration Interface
R
Otherwise, RDWR_B can be tied Low and BUSY can be ignored. Unlike earlier Virtex
devices, the BUSY signal never needs to be monitored when configuring Virtex-4 devices.
Refer to “Bitstream Loading (Steps 4-7)” in Chapter 1 and to Chapter 8.
Notes relevant to Figure 2-14:
1. The DONE pin is by default an open-drain output requiring an external pull-up
resistor. A 330Ω pull-up resistor is recommended. In this arrangement, the active
DONE driver must be disabled.
2. The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is
required.
3. The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.
4. The BUSY signals can be left unconnected if readback is not needed.
5. An external controller such as a microprocessor or CPLD is needed to control
configuration.
6. The CCLK net requires Thevenin parallel termination. See “Board Layout for
Configuration Clock (CCLK),” page 34.
Figure 2-14: Multiple Slave Device Configuration on an 8-bit SelectMAP Bus
PROGRAM
INIT
DONE
Virtex-4
Slave
SelectMAP
INIT_B
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
PROGRAM_B
DONE
M0
M1 M2
CS(1)
ug071_20_073007
Virtex-4
Slave
SelectMAP
INIT_B
D[0:7]
CCLK
RDWR_B
BUSY
CS_B
DATA[0:7]
CCLK
WRITE
BUSY
PROGRAM_B
DONE
M0
M1 M2
CS(0)
(1) (2)
(6)
(6)

Xilinx Virtex-4 Specifications

General

Brand	Xilinx
Model	Virtex-4
Category	Motherboard
Language	English