UG-1828 Preliminary Technical Data
Rev. PrC | Page 108 of 338
A hop frame entry is read at the channel setup rising edge, and the index to the table is incremented at the hop edge.
Figure 107, shows an example of automatic increment mode. This example has a 3-entry table. Reading of the entries is done by firmware
at the HOP edges. Before first rising edge of HOP signal table should be written into ADRV9001 memory by BBIC, and at the HOP edge
the table should be ready to be read by firmware.
Figure 107. Automatic Table Increment
Index by Pin
Rather than automatically incrementing through a frequency hopping table, the user can use up to 6 DGPIO pins to index any valid entry
in the hop table.
Figure 108. Index by Using DGPIO Pins
At initialization, the user can assign up to 6 DPGIO pins to provide 64 possible indices to a frequency hopping table.
During operation, the user should set the DGPIO pins prior to the upcoming HOP signal edge. User should make sure the DGPIO
signals are set and stable by the time HOP signal edge comes. ADRV9001 will sample the DGPIO pins at the HOP signal edge.
The following restrictions apply to this mode;
• Each DGPIO pin represents a bit in the index, the ADRV9001 samples each assigned pin to form a full index to the table.
• The ADRV9001 expects that the lower DPGIO number is the LSB of the index.
• Adjacent DGPIO pins must be assigned (for example, cannot assign DGPIO-0 to Bit 0, and DPGIO-11 to Bit 1, and so on).
• The ADRV9001 samples the DPGIO pins at every channel setup rising edge. It will use any index if the sampled index is deemed
valid (meaning, provide a valid index to the frequency hopping table).
Switching Between Two Frequency Hopping Tables
F3 F12
1
10 0
D1 D0
D3 D2
HOP
SIGNAL
CHANNEL
SETUP
NAVASSA SAMPLES
DGPIO, TAKING
INDEX OF C
NAVASSA SAMPLES
DGPIO, TAKING
INDEX OF 3
24159-486
BBIC SET
DPGIO = 0x3
0 0
1 1
D1 D0D3 D2
BBIC SET
DPGIO = 0xC
-485
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