Analog Devices ADRV9002 User Manual

Preliminary Technical Data UG-1828
Rev. PrC | Page 55 of 338
For I data duration and low for Q data duration. In the case of a 16-bit data sample, RX_STROBE is high for 16 clock cycles (I data
sample) and low for 16 clock cycles (Q data sample).
The Transmit CSSI Interface
The one-lane mode transmit CSSI interface of each channel (Tx1 and Tx2) is a 4-wire digital interface consisting of:
• TX_DCLK_IN: is an input clock synchronized to the data and strobe inputs.
• TX_STROBE_IN: is an input signal indicating the first bit of the serial data sample.
• TX_DATA_IN: is an input serial data stream.
• TX_DCLK_OUT: is an optional output reference clock that is provided to the baseband processor to generate all the above signals,
the baseband processor can also use RX_DCLK_OUT as the reference clock when its clock rate is equal with Transmit SSI clock
rate.
The I and Q samples can be deserialized starting with configurable I or Q first and MSB or LSB first, Figure 29 illustrates the Transmit
CSSI interface (Tx1 and Tx2) for a 16-bit I/Q data sample with I sample and MSB first configuration.
Figure 29. Transmit CSSI Timing for 16-Bit I/Q Data Sample (I and MSB First)
The TX_STROBE_IN signal is aligned with the first bit of the serialized data (I and Q), and can be configured to be high:
• For one clock cycle at start of I and Q sample transmit. In the case a 16-bit data sample, the TX_STROBE is high for one clock cycle
and low for 31 clock cycles.
• For I data duration and Low for Q data duration. In the case of a 16-bit data sample, TX_STROBE is high for 16 clock cycles (I data
sample) and low for 16 clock cycles (Q data sample).
CSSI Data Symbols Transmit and Receive
The previous sections described data transfer with I/Q format with 16bit width. When the ADRV9001 internal modulation/demodulation
is enabled (refer to the Transmitter Signal Chain and Rx Demodulator sections), the data transfer between ADRV9001 and baseband
processor would be 2 bits or 16 bits I only data (denoted as symbol to differentiate with I/Q complex samples). In a symbol format mode,
raw data are transferred through this interface using different data size. The CSSI interface supports three additional data formats:
• 2 bits of data
• 8 bits of data
• 16 bits of data
Data with a size of two bits could be transferred over a CSSI with an 8-bit data format with six dummy bits. The clock and strobe behavior
are similar to the I/Q format described in previous sections.
Figure 30 illustrates the receive CSSI interface (Rx) for 2-bit data symbols.
TX_DATA_IN
TX_DCLK_IN
TX_S
TRO
BE_IN
OR
TX_
STR
OBE_IN
I0_D15 I0_D14 I0_D0
Q0_D15 Q0_D14 I0_Q0 I1_D15
TX_DCLK_OUT
24159-026

Analog Devices ADRV9002 Specifications

General

Brand	Analog Devices
Model	ADRV9002
Category	Transceiver
Language	English