Introduction 1
1 – 5
• Extended Dynamic Range—Extended sums-of-products, common in DSP
algorithms, are supported in the multiply/accumulate units of the
ADSP-2100 family. A 40-bit accumulator provides eight bits of
protection against overflow in successive additions to ensure that no
loss of data or range occurs; 256 overflows would have to occur before
any data is lost. Special instructions are provided for implementing
block floating-point scaling of data.
• Single-Cycle Fetch of Two Operands—In extended sums-of-products
calculations, two operands are needed on each cycle to feed the
calculation. All members of the ADSP-2100 family are able to sustain
two-operand data throughput, whether the data is stored on-chip or
off.
• Hardware Circular Buffers—A large class of DSP algorithms, including
digital filters, requires circular data buffers. The ADSP-2100 family
base architecture includes hardware to handle address pointer
wraparound, simplifying the implementation of circular buffers both
on- and off-chip, and reducing overhead (thereby improving
performance).
• Zero-Overhead Looping and Branching—DSP algorithms are repetitive
and are most logically expressed as loops. The program sequencer in
the ADSP-2100 family supports looped code with zero overhead,
combining excellent performance with the clearest program structure.
Likewise, there are no overhead penalties for conditional branches.
1.2 CORE ARCHITECTURE
This section describes the core architecture of the ADSP-2100 family, as
shown in Figure 1.1. Each component of the core architecture is described
in detail in different chapters of this manual, as shown below:
Arithmetic/logic unit (ALU) Chapter 2, Computation Units
Multiplier/accumulator (MAC) Chapter 2, Computation Units
Barrel shifter Chapter 2, Computation Units
Program sequencer Chapter 3, Program Control
Status registers and stacks Chapter 3, Program Control
Two data address generators (DAGs) Chapter 4, Data Transfer
PMD-DMD bus exchange (PX registers) Chapter 4, Data Transfer
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