10Memory Interface
10 – 17
1514131211109876543210
System Control Register
BPAGE (Boot Page Select)
Default = 0
BWAIT (Boot Wait States)
Default=3 for ADSP-21xx
Default=7 for ADSP-2171, ADSP-21msp58
BFORCE
(Boot Force Bit)
000
DM(0x3FFF)
0000/111
Figure 10.17 Boot Control Fields In System Control Register
10.4.3 Boot Memory Access
The processor can boot its internal memory from a single byte-wide
CMOS EPROM, such as the 27C64 and 27C512. A low-cost, commodity-
grade EPROM with an industry-standard access time can be used. The
number of wait states for the boot memory access is selected in the BWAIT
field of the System Control Register (see Figure 10.17). This field can be set
to any value from 0 to 7 in order to generate 0 to 7 wait states. The default
value at reset is 3 wait states on the ADSP-2101, ADSP-2105, ADSP-2111,
and ADSP-2115. BWAIT defaults to 7 wait states on the ADSP-2171 and
ADSP-21msp58.
Timing of the boot memory access is identical to that of external program
memory or external data memory accesses, except that the active strobe is
BMS
rather than
PMS
or
DMS
. To address eight pages of 8K bytes each, 16
bits are needed. The least significant 14 bits are output on the 14-bit
address bus, and the most significant 2 bits are output on the 2 MSBs of
the data bus during a boot memory access. Data is read from the middle
eight bits of the data bus.
10.4.4 Boot Loading Sequence
The order in which the processor loads data into its internal memory
during a boot operation is unimportant in most applications. The boot
loading sequence is explained in this section for those instances in which
the order is relevant, for instance when a latch is providing data rather
than an EPROM.
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