15 Instruction Set Reference
15 –16
15.8 MISCELLANEOUS INSTRUCTIONS
There are several miscellaneous instructions. NOP is a no operation
instruction. The PUSH/POP instructions allows you to explicitly control
the status, counter, PC and loop stacks; interrupt servicing automatically
pushes and pops some of these stacks.
The Mode Control instruction enables and disables processor modes of
operation: bit-reversal on DAG1, latching ALU overflow, saturating the
ALU result register, choosing the primary or secondary register set, GO
mode for continued operation during bus grant, multiplier shift mode for
fractional or integer arithmetic, and timer enabling.
A single ENA or DIS can be followed by any number of mode identifiers,
separated by commas; ENA and DIS can also be repeated. All seven
modes can be enabled, disabled, or changed in a single instruction.
The MODIFY instruction modifies the address pointer in the I register
selected with the value in the selected M register, without performing any
actual memory access. As always, the I and M registers must be from the
same DAG; any of I0-I3 may be used only with one from M0-M3 and the
same for I4-I7 and M4-M7. If circular buffering is in use, modulus logic
applies (See Chapter 4, “Data Transfer,” for more information).
The FO (Flag Out), FL0, FL1 and FL2 pins can each be set, cleared, or
toggled. This instruction provides a control structure for multiprocessor
communication.
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