Analog Devices adsp-2100 User Manual

CHAPTER 1 INTRODUCTION
1.1 OVERVIEW ........................................................................................ 1–1
1.1.1 Functional Units........................................................................... 1–1
1.1.2 Memory And System Interface .................................................. 1–3
1.1.3 Instruction Set .............................................................................. 1–4
1.1.4 DSP Performance ......................................................................... 1–4
1.2 CORE ARCHITECTURE .................................................................. 1–5
1.2.1 Computational Units................................................................... 1–6
1.2.2 Address Generators & Program Sequencer ............................. 1–7
1.2.3 Buses ........................................................................................ 1–8
1.3 ON-CHIP PERIPHERALS ................................................................ 1–8
1.3.1 Serial Ports .................................................................................... 1–8
1.3.2 Timer ........................................................................................ 1–9
1.3.3 Host Interface Port....................................................................... 1–9
1.3.4 DMA Ports .................................................................................... 1–9
1.3.5 Analog Interface......................................................................... 1–10
1.4 ADSP-2100 FAMILY DEVELOPMENT TOOLS ......................... 1–10
1.5 ORGANIZATION OF THIS MANUAL ....................................... 1–11
CHAPTER 2 COMPUTATIONAL UNITS
2.1 OVERVIEW ........................................................................................ 2–1
2.1.1 Binary String................................................................................. 2–1
2.1.2 Unsigned ....................................................................................... 2–1
2.1.3 Signed Numbers: Twos-Complement ...................................... 2–1
2.1.4 Fractional Representation: 1.15.................................................. 2–2
2.1.5 ALU Arithmetic ........................................................................... 2–2
2.1.6 MAC Arithmetic .......................................................................... 2–3
2.1.7 Shifter Arithmetic ........................................................................ 2–3
2.1.8 Summary ....................................................................................... 2–4
2.2 ARITHMETIC/LOGIC UNIT (ALU).............................................. 2–5
2.2.1 ALU Block Diagram Discussion ................................................ 2–5
2.2.2 Standard Functions...................................................................... 2–7
2.2.3 ALU Input/Output Registers .................................................... 2–8
2.2.4 Multiprecision Capability........................................................... 2–8
2.2.5 ALU Saturation Mode ................................................................. 2–8
2.2.6 ALU Overflow Latch Mode ....................................................... 2–9
Contents
iii

Analog Devices adsp-2100 Specifications

General

Brand	Analog Devices
Model	adsp-2100
Category	Computer Hardware
Language	English

Summary

CHAPTER 1 INTRODUCTION

1.1 OVERVIEW

Introduction to the ADSP-2100 family architecture, DSP optimization, and manual scope.

1.1.1 Functional Units

1.1.2 Memory And System Interface

1.2 CORE ARCHITECTURE

Describes the core components: ALU, MAC, Shifter, DAGs, Program Sequencer.

CHAPTER 2 COMPUTATIONAL UNITS

2.1 OVERVIEW

Introduces the three computational units: ALU, MAC, and Barrel Shifter, and number formats.

2.1.6 MAC Arithmetic

2.2 ARITHMETIC/LOGIC UNIT (ALU)

Details the ALU's standard arithmetic and logic functions.

2.2.1 ALU Block Diagram Discussion

2.2.7 Division

2.3 MULTIPLIER/ACCUMULATOR (MAC)

Covers MAC's high-speed multiplication, accumulation, and saturation functions.

2.3.1 MAC Block Diagram Discussion

2.3.2 MAC Operations

2.4 BARREL SHIFTER

Describes the shifter's functions: arithmetic, logical shifts, normalization, exponent derivation.

2.4.1 Shifter Block Diagram Discussion

CHAPTER 3 PROGRAM CONTROL

3.1 OVERVIEW

Describes the program sequencer, interrupt controller, and status/condition logic.

3.2 PROGRAM SEQUENCER

Explains how the sequencer generates instruction addresses and controls program flow.

3.2.1 Next Address Select Logic

3.2.2 Program Counter & PC Stack

3.2.3 Loop Counter & Stack

3.2.4 Loop Comparator & Stack

3.3.1 JUMP Instruction

3.3.2 CALL Instruction

3.3.3 DO UNTIL Loops

3.4 INTERRUPTS

Explains how the program sequencer responds to interrupts by vectoring to appropriate addresses.

3.4.1 Interrupt Servicing Sequence

3.4.2 Configuring Interrupts

Details registers used for interrupt configuration: ICNTL, IMASK, IFC.

3.4.3 Interrupt Latency

3.5 STATUS REGISTERS & STATUS STACK

Describes status registers (ASTAT, SSTAT, MSTAT) and the status stack.

3.5.1 Arithmetic Status Register (ASTAT)

3.5.3 Mode Status Register (MSTAT)

3.6 CONDITIONAL INSTRUCTIONS

CHAPTER 4 DATA TRANSFER

4.1 OVERVIEW

Describes processor units controlling data movement and bus exchange.

4.2 DATA ADDRESS GENERATORS (DAGS)

Explains the two independent DAGs for indirect addressing and automatic address modification.

4.2.1 DAG Registers

4.2.3 Modulo Addressing (Circular Buffers)

4.3 PROGRAMMNG DATA ACCESSES

4.3.2 Circular Buffers

4.4 PMD-DMD BUS EXCHANGE

CHAPTER 5 SERIAL PORTS

5.1 OVERVIEW

Describes synchronous serial ports (SPORTS) for serial data communications and interconnections.

5.2.1 Interrupts

5.2.2 SPORT Operation

5.3 SPORT PROGRAMMING

Describes programming SPORT configuration registers and data section.

5.3.1 SPORT Configuration

Explains how to accomplish SPORT configuration by setting bit and field values in registers.

5.3.2 Receiving And Transmitting Data

5.5 SERIAL CLOCKS

5.10 COMPANDING AND DATA FORMAT

5.11 AUTOBUFFERING

Details autobuffering mechanism for receiving/transmitting entire data blocks.

5.12 MULTICHANNEL FUNCTION

5.13 SPORT TIMING CONSIDERATIONS

5.13.6 Interrupt & Autobuffer Synchronization

CHAPTER 6 TIMER

6.1 OVERVIEW

Introduces the programmable interval timer for generating periodic interrupts.

6.2 TIMER ARCHITECTURE

Details timer registers TCOUNT, TPERIOD, TSCALE, and mode control.

6.3 RESOLUTION

6.4 TIMER OPERATION

CHAPTER 7 HOST INTERFACE PORT

7.1 OVERVIEW

Introduces HIP as a parallel I/O port for using processors as memory-mapped peripherals.

7.3 HIP FUNCTIONAL DESCRIPTION

Details HIP's three functional blocks: HCI, data registers (HDRs), and status registers (HSRs).

7.4 HIP OPERATION

Explains how the ADSP-21xx core and host computer interact via HDRs.

7.4.1.1 HIP Status Synchronization

7.4.2 Interrupt-Driven Operation

7.5 HIP INTERRUPTS

Covers HIP interrupts, their masking via IMASK/HMASK, and vector locations.

7.6 HOST INTERFACE TIMING

7.7 BOOT LOADING THROUGH THE HIP

Explains loading internal program RAM using a boot sequence via HIP.

CHAPTER 8 ANALOG INTERFACE

8.1 OVERVIEW

Introduces the analog signal interface with ADC, DAC, filters, and registers.

8.2 A/D CONVERSION

Details the A/D conversion circuitry including input multiplexer, PGA, and ADC.

8.2.2 ADC

Describes the ADC components: sigma-delta modulator, decimation filter, and digital high pass filter.

8.3 D/A CONVERSION

Covers the D/A conversion circuitry including DAC, smoothing filter, PGA, and output amplifier.

8.3.1 DAC

Details the DAC's digital filters, sigma-delta modulator, and transmit data register.

8.4 OPERATING THE ANALOG INTERFACE

Describes operating the analog interface using memory-mapped control and data registers.

8.4.1 Memory-mapped Control Registers

Details the analog control register and analog autobuffer/powerdown register.

8.4.1.1 Analog Control Register

Explains the analog control register for configuring ADC/DAC settings.

8.4.1.2 Analog Autobuffer/Powerdown Register

8.4.3 ADC & DAC Interrupts

8.5 CIRCUIT DESIGN CONSIDERATIONS

8.5.1 Analog Signal Input

Shows recommended input circuit with low-pass filter and PGA.

8.5.2 Analog Signal Output

CHAPTER 9 SYSTEM INTERFACE

9.1 OVERVIEW

Describes basic system interface features, hardware, and software for DSP processors.

9.2 CLOCK SIGNALS

Explains operation with TTL-compatible clock input or external crystal.

9.3 RESET

Explains the RESET signal's function for halting execution and performing a hardware reset.

9.4 SOFTWARE FORCED REBOOTING

9.5 EXTERNAL INTERRUPTS

Covers prioritized, individually maskable external interrupts (level- or edge-triggered).

9.7 POWERDOWN

Describes the powerdown feature for entering a low-power dormant state.

9.7.1 Powerdown Control

Explains control parameters for powerdown operation via SPORT1 Autobuffer/Powerdown Control Register.

9.7.2 Entering Powerdown

Details the sequence for initiating and entering powerdown mode using PWD pin or PDFORCE bit.

9.7.3 Exiting Powerdown

Explains methods for exiting powerdown using PWD pin or RESET, and specifying start-up modes.

9.7.3.1 Ending Powerdown With The PWD Pin

9.7.3.2 Ending Powerdown With The RESET Pin

9.7.5 Processor Operation During Powerdown

9.7.5.4 IDMA Port During Powerdown (ADSP-2181)

9.7.5.6 BDMA Port During Powerdown (ADSP-2181)

9.7.6 Conditions For Lowest Power Consumption

CHAPTER 10 MEMORY INTERFACE

10.1 OVERVIEW

Describes the modified Harvard architecture, on-chip memory, and boot memory space.

10.2 PROGRAM MEMORY INTERFACE

Details the program memory interface for all ADSP-21xx processors except ADSP-2181.

10.2.1 External Program Memory Read / Write

10.2.2 Program Memory Maps

10.3 DATA MEMORY INTERFACE

Describes the data memory interface for all ADSP-21xx processors except ADSP-2181.

10.3.1 External Data Memory Read/Write

10.3.2 Data Memory Maps

10.4 BOOT MEMORY INTERFACE

Describes the boot memory interface for loading internal program memory from external sources.

10.4.2 Powerup Boot & Software Reboot

10.4.3 Boot Memory Access

10.5 BUS REQUEST / GRANT

Describes bus request and grant feature for relinquishing bus control to external devices.

10.6 ADSP-2181 MEMORY INTERFACES

Details ADSP-2181 specific memory features like overlay, I/O, byte memory, and IDMA.

10.6.1 ADSP-2181 Program Memory Interface

Explains ADSP-2181 program memory addressing and overlay capabilities.

10.6.2 ADSP-2181 Data Memory Interface

Details ADSP-2181 data memory addressing, overlays, and wait states.

10.6.3 ADSP-2181 Byte Memory Interface

10.6.4 ADSP-2181 I/O Memory Space

10.6.6 External Memory Read – Overlays & I/O Memory

10.6.7 External Memory Write – Overlays & I/O Memory

CHAPTER 11 DMA PORTS

11.1 OVERVIEW

Introduces ADSP-2181 DMA interfacing features: BDMA and IDMA.

11.2 BDMA PORT

Covers BDMA port's 8-bit wide byte memory space for program code or data.

11.2.1 BDMA Port Functional Description

Explains how BDMA port loads/stores program instructions and data from/to byte memory.

11.2.2 BDMA Control Registers

Details memory-mapped registers for setup and control of BDMA transfers.

11.2.4 BDMA Booting

Covers loading on-chip program memory from external source using byte memory booting.

11.3 IDMA PORT

Describes IDMA port as a parallel I/O port for accessing internal memory by host systems.

11.3.2 IDMA Port Functional Description

Explains how IDMA port lets host systems access internal memory locations.

11.3.4 IDMA Timing

11.3.4.2 Long Read Cycle

11.3.4.3 Short Read Cycle

11.3.4.4 Long Write Cycle

11.3.4.5 Short Write Cycle

11.3.5 Boot Loading Through The IDMA Port

Covers booting through the IDMA port using specific reset and pin settings.

11.3.6 DMA Cycle Stealing, DMA Hold Offs, and IACK Acknowledge

CHAPTER 12 PROGRAMMING MODEL

12.1 OVERVIEW

Introduces ADSP-21xx processors from a programming standpoint: units, registers, peripherals.

12.1.1 Data Address Generators

Details DAG registers (I, M, L) for pointers, modification, and circular buffers.

12.1.2 Program Sequencer

Covers registers controlling subroutines, loops, interrupts, and mode selection.

12.1.2.1 Interrupts

Details ICNTL, IFC, and IMASK registers for interrupt control.

12.1.2.2 Loop Counts

12.1.2.3 Status And Mode Bits

Describes stack status (SSTAT), arithmetic status (ASTAT), and mode status (MSTAT) registers.

12.1.2.4 Stacks

12.1.3 Computational Units

Describes registers for ALU, MAC, and Shifter units.

12.1.6 Serial Ports

Covers SPORT registers for control, companding, and autobuffering.

12.1.7 Memory Interface & SPORT Enables

12.1.8 Host Interface

Describes HIP registers: data, status, and interrupt mask registers.

12.1.9 Analog Interface

Lists memory-mapped registers for the analog interface (ADC, DAC, control).

CHAPTER 13 HARDWARE EXAMPLES

13.1 OVERVIEW

13.2 BOOT LOADING FROM HOST USING BUS REQUEST & GRANT

Shows a simple way to download programs from a host via memory interface using bus request/grant.

13.3 SERIAL PORT TO CODEC INTERFACE

Details interfacing a codec with ADSP-21xx serial ports for analog-to-digital conversion.

13.4 SERIAL PORT TO DAC INTERFACE

Explains sending DSP process output analog information directly to a DAC via serial port.

13.5 SERIAL PORT TO ADC INTERFACE

Describes receiving analog signals into digital samples via serial port from an ADC.

13.6 SERIAL PORT TO SERIAL PORT INTERFACE

CHAPTER 14 SOFTWARE EXAMPLES

14.1 OVERVIEW

14.2 SYSTEM DEVELOPMENT PROCESS

Outlines the development process using tools like System Builder, Assembler, Linker, Simulators.

14.3 SINGLE-PRECISION FIR TRANSVERSAL FILTER

Explains FIR transversal filter structure obtained from discrete-time convolution equation.

14.4 CASCADED BIQUAD IIR FILTER

14.6 SINGLE-PRECISION MATRIX MULTIPLY

14.7 RADIX-2 DECIMATION-IN-TIME FFT

Describes the FFT program with subroutines for scrambling, FFT computation, and scaling.

14.7.2 DIT FFT Subroutine

14.7.3 Bit-Reverse Subroutine

14.7.4 Block Floating-Point Scaling Subroutine

CHAPTER 15 INSTRUCTION SET REFERENCE

15.1 QUICK LIST OF INSTRUCTIONS

Provides a complete reference organized by instruction group and individual instruction.

15.2 OVERVIEW

Gives an overview and detailed reference for the ADSP-2100 family instruction set.

15.3 INSTRUCTION TYPES & NOTATION CONVENTIONS

15.4 MULTIFUNCTION INSTRUCTIONS

Illustrates the power of multifunction instructions combining data moves and computations.

15.4.1 ALU/MAC With Data & Program Memory Read

Explains the sum-of-products operation common in DSP algorithms.

15.4.3 Computation With Memory Read

15.4.4 Computation With Memory Write

15.4.5 Computation With Data Register Move

15.5 ALU, MAC & SHIFTER INSTRUCTIONS

Groups instructions for computations in ALU, MAC, and Shifter units.

15.5.1 ALU Group

15.5.2 MAC Group

15.5.3 Shifter Group

15.6 MOVE: READ & WRITE

Explains how MOVE instructions move data to and from registers and memory.

15.7 PROGRAM FLOW CONTROL

Covers instructions like JUMP, CALL, DO UNTIL, and IDLE for controlling program flow.

15.9 EXTRA CYCLE CONDITIONS

15.10 INSTRUCTION SET SYNTAX

APPENDIX A INSTRUCTION CODING

A.1 OPCODES

Gives a summary of the complete instruction set, defining opcode field names.

A.2 ABBREVIATION CODING

APPENDIX B DIVISION EXCEPTIONS

B.1 DIVISION FUNDAMENTALS

Describes the non-restoring divide algorithm, operands, and cycle counts.

B.1.1 Signed Division

B.1.2 Unsigned Division

B.2 ERROR CONDITIONS

B.2.1 Negative Divisor Error

APPENDIX C NUMERIC FORMATS

C.1 OVERVIEW

Introduces 16-bit fixed-point data support and block floating-point format.

C.4 BINARY MULTIPLICATION

C.4.1 Fractional Mode And Integer Mode

C.5 BLOCK FLOATING-POINT FORMAT

Enables fixed-point processor to gain dynamic range of floating-point without overhead.

APPENDIX D INTERRUPT VECTOR ADDRESSES

D.1 INTERRUPT VECTOR ADDRESSES

Lists interrupts and associated vector addresses for each ADSP-2100 family processor.