15Instruction Set Reference
15 – 3
The 24-bit instruction word allows a high degree of parallelism in
performing operations. The instruction set allows for single-cycle
execution of any of the following combinations:
• any ALU, MAC or Shifter operation (conditional or non-conditional)
• any register-to-register move
• any data memory read or write
• a computation with any data register to data register move
• a computation with any memory read or write
• a computation with a read from two memories.
The instruction set allows maximum flexibility. It provides moves from
any register to any other register, and from most registers to/from
memory. In addition, almost any ALU, MAC or Shifter operation may be
combined with any register-to-register move or with a register move to or
from either internal or external memory.
15.3 INSTRUCTION TYPES & NOTATION CONVENTIONS
The ADSP-2100 family instruction set is grouped into the following
categories:
• Computational: ALU, MAC, Shifter
• Move
• Program Flow
• Multifunction
• Miscellaneous
Because the multifunction instructions best illustrate the power of the
processors’ architecture, in the next section we begin with a discussion of
this group of instructions.
Throughout this chapter you will find tables summarizing the syntax of
the instruction groups. The following notation conventions are used in
these tables and in the reference page for each instruction.
Square Brackets [ ] Anything within square brackets is an optional
part of the instruction statement.
Parallel Lines | | Lists of operands are enclosed by vertical parallel
bars. One of the operands listed must be chosen.
If the parallel bars are within square brackets,
then the operand is optional for that instruction.
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