Program Control3
3 – 10
Execution of the DO UNTIL instruction pushes the address of the
instruction immediately following the DO UNTIL onto the PC stack (by
pushing the incremented PC). On the same cycle, the loop stack is pushed
with the address of the end-of-loop instruction and the termination
condition.
As execution continues within the loop, the loop comparator checks each
instruction’s address against the address of the loop’s last instruction.
Until that address is reached, normal execution continues.
Each time the end of the loop is reached, the loop comparator determines
that the currently executing instruction is the last in the loop. This affects
the next address select logic of the program sequencer: instead of using
the incremented PC for the next address, the loop termination condition is
evaluated. If the termination condition is false, execution continues with
the first instruction of the loop (the top of the PC stack is taken as the next
address). Note that the PC and loop stacks are not popped, only read.
On the final pass through the loop, the termination condition is true. The
PC stack is popped and execution continues with the instruction
immediately following the last instruction of the loop. The loop stack and
count stack are also popped on this cycle.
3.3.4 IDLE Instruction
The IDLE instruction causes the processor to wait indefinitely in a low
power state until an interrupt occurs. When an unmasked interrupt
occurs, it is serviced; execution then continues with the instruction
following the IDLE instruction.
3.3.4.1 Slow IDLE
An enhanced version of the IDLE intruction allows the processor’s
internal clock signal to be slowed, further reducing power consumption.
The reduced clock frequency, a programmable fraction of the normal clock
rate, is specified by a selectable divisor given in the IDLE instruction. The
format of the instruction is
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the processor fully
functional, but operating at the slower clock rate. While it is in this state,
the processor’s other internal clock signals, such as SCLK, CLKOUT, and
timer clock, are reduced by the same ratio. The default form of the
instruction, when no clock divisor is given, is the standard IDLE
instruction.
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