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Syntax: [ IF cond ] SR = [SR OR] ASHIFT xop (HI) ;
(LO)
Permissible xops Permissible conds (see Table 15.9)
SI AR EQ LE AC
SR1 MR2 NE NEG NOT AC
SR0 MR1 GT POS MV
MR0 GE AV NOT MV
LT NOT AV NOT CE
Example: IF LT SR = SR OR ASHIFT SI (LO);
Description: Test the optional condition and, if true, then perform the
designated arithmetic shift. If the condition is not true then perform a no-
operation. Omitting the condition performs the shift unconditionally. The
operation arithmetically shifts the bits of the operand by the amount and
direction specified in the Shift Code from the SE register. Positive Shift
Codes cause a left shift (upshift) and negative codes cause a right shift
(downshift).
The shift may be referenced to the upper half of the output field (HI
option) or to the lower half (LO option). The shift output may be logically
ORed with the present contents of the SR register by selecting the SR OR
option.
For ASHIFT with a positive Shift Code (i.e. positive value in SE), the
operand is shifted left; with a negative Shift Code (i.e. negative value in
SE), the operand is shifted right. The number of positions shifted is the
count in the Shift Code. The 32-bit output field is sign-extended to the left
(the MSB of the input is replicated to the left), and the output is zero-filled
from the right. Bits shifted out of the high order bit in the 32-bit
destination field (SR
31
) are dropped. Bits shifted out of the low order bit in
the destination field (SR
0
) are dropped.
To shift a double precision number, the same Shift Code is used for both
halves of the number. On the first cycle, the upper half of the number is
shifted using an ASHIFT with the HI option; on the following cycle, the
lower half of the number is shifted using an LSHIFT with the LO and OR
options. This prevents sign bit extension of the lower word’s MSB.
Status Generated: None affected.
SHIFTER
ARITHMETIC SHIFT
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