5 Serial Ports
5 – 4
interrupt inputs, I
RQ0 and IRQ1, and the Flag In and Flag Out signals
instead of as a serial port. The internally generated serial clock may
still be used in this configuration. See Section 5.4.
5.2.1 Interrupts
Each SPORT has a receive interrupt and a transmit interrupt. The priority
of these interrupts is shown in Table 5.2.
Highest SPORT0 Transmit (on 2-SPORT processors)
SPORT0 Receive (on 2-SPORT processors)
SPORT1 Transmit
Lowest SPORT1 Receive
Table 5.2 SPORT Interrupt Priorities
For complete details about how interrupts are handled, see the
“Interrupts” section in Chapter 3, “Program Control.”
5.2.2 SPORT Operation
Writing to a SPORT’s TX register readies the SPORT for transmission; the
TFS signal initiates the transmission of serial data. Once transmission has
begun, each value written to the TX register is transferred to the internal
transmit shift register and subsequently the bits are sent, MSB first. Each
bit is shifted out on the rising edge of SCLK.
After the first bit (MSB) of a word has been transferred, the SPORT
generates the transmit interrupt. The TX register is now available for the
next data word, even though the transmission of the first word is ongoing.
In the receiving section, bits accumulate as they are received in an internal
receive register. When a complete word has been received, it is written to
the RX register and the receive interrupt for that SPORT is generated.
Interrupts are generated differently if autobuffering is enabled; see
“Autobuffering” later in this chapter.
5.3 SPORT
PROGRAMMING
To the programmer, the SPORT can be viewed as two functional sections.
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