Analog Devices adsp-2100 User Manual

11DMA Ports
11 – 17
11.3.4 IDMA Timing
From the host system interface point of view, there are three IDMA port
operations with critical timing parameters. These operations are:
• latching the IDMA internal memory address,
• reading from the IDMA port, and
• writing to the IDMA port.
The following sections cover the timing details of each of these operations.
11.3.4.1 Address Latch Cycle
The host writes the DMA starting address and destination memory type
(DM or PM) using the IDMA address latch cycle. The address latch cycle,
shown in Figure 11.9, consists of the following steps:
1. Host ensures that
IACK line is low.
2. Host asserts IAL and
IS , directing the ADSP-2181 to latch the IDMA
starting address from the IAD15-0 address/data bus into the IDMA
Control Register.
3. Host drives the starting address (bits 0-13) and destination memory
type (bit 14) onto the IAD15-0 bus. (Bit 15 must be a 0.)
Note that
IRD and IWR remain high (inactive) throughout the latch
operation.
IACK
IAL
IS
IAD15-0 ADDRESS
Figure 11.9 IDMA Address Latch Cycle Timing

Analog Devices adsp-2100 Specifications

General

Brand	Analog Devices
Model	adsp-2100
Category	Computer Hardware
Language	English