8Analog Interface
8 – 9
8.4 OPERATING THE ANALOG INTERFACE
The analog interface of the ADSP-21msp58/59 is operated with the use
of several memory-mapped control and data registers. The ADC and
DAC I/O data can be received and transmitted in two memory-
mapped data registers. The data can also be autobuffered into (and
from) on-chip memory where data is automatically transferred to or
from the data registers. In both cases, the I/O processing is interrupt-
driven: two ADSP-21msp58/59 interrupts are dedicated to the analog
interface, one for ADC receive data and one for DAC transmit data.
(Note: Autobuffering with SPORT1 is not available on the
ADSP-21msp5x processors because this autobuffering channel is used
for the analog interface.)
The ADSP-21msp58/59 must have an input clock frequency of 13
MHz. At this frequency, analog-to-digital and digital-to-analog
converted data is transmitted at an 8 kHz rate with a single 16-bit word
transmitted every 125 µs.
8.4.1 Memory-Mapped Control Registers
Two memory-mapped control registers are used to configure the
ADSP-21msp58/59’s analog interface: the analog control register and
analog autobuffer/powerdown register.
8.4.1.1 Analog Control Register
The analog control register (located at address 0x3FEE in data
memory) is shown in Figure 8.4. This register configures the ADC
input multiplexer, ADC input gain PGA, ADC high pass filter, DAC
high pass filter, and DAC output gain PGA.
The analog control register also contains the APWD bits (bits 5, 6)
which must both be set to ones to enable and start up the analog
interface—always enable and disable the analog interface using both bits
5 and 6. The DAC and ADC begin transmitting data after these bits are
set. Clearing the APWD bits disables the entire analog interface by
putting it in a powerdown state. The APWD bits must be cleared (to
zeros) at least three processor cycles before putting the processor in
powerdown. See “Powerdown” in Chapter 9, System Interface.
The analog control register is cleared (to 0x0000) by the processor’s
RESET
signal. Note that bits 10-15 of this register are reserved and
must always be set to zero.
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