System Interface9
9 – 14
9.5 EXTERNAL
INTERRUPTS
Each ADSP-2100 family processor has a number of prioritized, individually
maskable external interrupts which can be either level- or edge-triggered.
These interrupt request pins are named
IRQ0, IRQ1, and IRQ2. The IRQ0 and
IRQ1 pins are only available as the (optional) alternate configuration of
SPORT1. The configuration of SPORT1 as either a serial port or as interrupts
(and flags) is determined by bit 10 of the processor’s system control register.
The ADSP-2181 processor additionally has two dedicated level-triggered
interrupt request pins and one dedicated edge-triggered interrupt request pin;
these are
IRQL0 , IRQL1, and IRQE.
Internal interrupts, including serial port, timer, host interface port, DMA and
analog interface interrupts, are discussed in other chapters. Additional
information about interrupt masking, set up, and operation can be found in
Chapter 3, “Program Control.”
9.5.1 Interrupt Sensitivity
Individual external interrupts can be configured in the ICNTL register as
either level-sensitive or edge-sensitive.
Level-sensitive interrupts operate by asserting the interrupt request line
(
IRQx) until the request is recognized by the processor. Once recognized, the
request must be deasserted before unmasking the interrupt so that the DSP
does not continually respond to the interrupt.
In contrast, edge-triggered interrupt requests are latched when any high-to-
low transition occurs on the interrupt line. The processor latches the interrupt
so that the request line may be held at any level for an arbitrarily long period
between interrupts. This latch is automatically cleared when the interrupt is
serviced. Edge-triggered interrupts require less external hardware than level-
sensitive requests since there is never a need to hold or negate the request.
With level-sensitive interrupts, however, many interrupting devices can share
a single request input; this allows easy system expansion.
An interrupt request will be serviced if it is not masked (in the IMASK
register) and a higher priority request is not pending. Valid requests initiate
an interrupt servicing sequence that vectors the processor to the appropriate
interrupt vector address. The interrupt vector addresses for each family
processor are given in Appendix D. There is a synchronization delay
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