15 Instruction Set Reference
15 –14
Registers: reg
SB Data Registers: dreg
PX
I0 – I7, M0 – M7, L0 – L7 AX0, AX1, AY0, AY1, AR
CNTR MX0, MX1, MY0, MY1, MR0, MR1, MR2
ASTAT, MSTAT, SSTAT SI, SE, SR0, SR1
IMASK, ICNTL, IFC
TX0, TX1, RX0, RX1
Table 15.7 Processor Registers: reg & dreg
15.7 PROGRAM FLOW CONTROL
Program flow control on the ADSP-2100 family processors is simple but
powerful. Here is an example of one instruction:
IF EQ JUMP my_label;
JUMP, of course, is a familiar construct from many other languages. My_label
is any identifier you wish to use as a label for the destination jumped to.
Instead of the label, an index register in DAG2 may be explicitly used. The
default scope for any label is the source code module in which it is declared.
The assembler directive .ENTRY makes a label visible as an entry point for
routines outside the module. Conversely, the .EXTERNAL directive makes it
possible to use a label declared in another module.
If the counter condition (CE, NOT CE) is to be used, an assignment to CNTR
must be executed to initialize the counter value. JUMP and CALL permit the
additional conditionals “FLAG_IN” and “NOT FLAG_IN” to be used for
branching on the state of the FI pin, but only with direct addressing, not with
DAG2 as the address source.
RTS (return from subroutine) and RTI (return from interrupt) provide for
conditional return from CALL or interrupt vectors respectively.
The IDLE instruction provides a way to wait for interrupts. IDLE causes the
processor to wait in a low-power state until an interrupt occurs. When an
interrupt is serviced, control returns to the instruction following the IDLE
statement. IDLE uses less power than loops created with JUMP.
Table 15.8 gives a summary of all program flow control instructions. The
condition codes are described in Table 15.9.
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