Computational Units
2 – 3
2
2.1.6 MAC Arithmetic
The multiplier produces results that are binary strings. The inputs are
“interpreted” according to the information given in the instruction itself
(signed times signed, unsigned times unsigned, a mixture, or a rounding
operation). The 32-bit result from the multiplier is assumed to be signed,
in that it is sign-extended across the full 40-bit width of the MR register
set.
The ADSP-2100 family supports two modes of format adjustment: the
fractional mode for fractional operands, 1.15 format (1 signed bit, 15
fractional bits), and the integer mode for integer operands, 16.0 format.
When the processor multiplies two 1.15 operands, the result is a 2.30
(2 sign bits, 30 fractional bits) number. In the fractional mode, the MAC
automatically shifts the multiplier product (P) left one bit before
transferring the result to the multiplier result register (MR). This shift
causes the multiplier result to be in 1.31 format, which can be rounded to
1.15 format. Figure 2.7, in the MAC section of this chapter, shows this.
In the integer mode, the left shift does not occur. For example, if the
operands are in the 16.0 format, the 32-bit multiplier result would be in
32.0 format. A left shift is not needed; it would change the numerical
representation. Figure 2.8 in the MAC section of this chapter shows this.
2.1.7 Shifter Arithmetic
Many operations in the shifter are explicitly geared to signed (twos-
complement) or unsigned values: logical shifts assume unsigned-
magnitude or binary string values and arithmetic shifts assume twos-
complement.
The exponent logic assumes twos-complement numbers. The exponent
logic supports block floating-point, which is also based on twos-
complement fractions.
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