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SHIFTER
NORMALIZE
Syntax: [ IF cond ] SR = [SR OR] NORM xop (HI) ;
(LO)
Permissible xops Permissible conds (see Table 15.9)
SI AR EQ LE AC
SR1 MR2 NE NEG NOT AC
SR0 MR1 GT POS MV
MR0 GE AV NOT MV
LT NOT AV NOT CE
Example: SR = NORM SI (HI) ;
Description: Test the optional condition and, if true, then perform the
designated normalization. If the condition is not true then perform a no-
operation. Omitting the condition performs the normalize
unconditionally. The operation arithmetically shifts the input operand to
eliminate all but one of the sign bits. The amount of the shift comes from
the SE register. The SE register may be loaded with the proper Shift Code
to eliminate the redundant sign bits by using the Derive Exponent
instruction; the Shift Code loaded will be the negative of the quantity: (the
number of sign bits minus one).
The shift may be referenced to the upper half of the output field (HI
option) or to the lower half (LO option). The shift output may be logically
ORed with the present contents of the SR register by selecting the SR OR
option. When the LO reference is selected, the 32-bit output field is zero-
filled to the left. Bits shifted out of the high order bit in the 32-bit
destination field (SR
31
) are dropped.
The 32-bit output field is zero-filled from the right. If the exponent of an
overflowed ALU result was derived with the HIX modifier, the 32-bit
output field is filled from left with the ALU Carry (AC) bit in the
Arithmetic Status Register (ASTAT) during a NORM (HI) operation. In
this case (SE=1 from the exponent detection on the overflowed ALU
value) a downshift occurs.
To normalize a double precision number, the same Shift Code is used for
both halves of the number. On the first cycle, the upper half of the number
is shifted using the HI option; on the following cycle, the lower half of the
number is shifted using the LO and OR options.
Status Generated: None affected.
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