3Program Control
3 – 15
Edge-sensitive interrupt inputs generally require less external hardware
than level-sensitive inputs, and allow signals such as sampling-rate clocks
to be used as interrupts.
A level-sensitive interrupt must remain asserted until the interrupt is
serviced. The interrupting device must then deassert the interrupt request
so that the interrupt is not serviced again. Level-sensitive inputs, however,
allow many interrupt sources to use the same input by combining them
logically to produce a single interrupt request. Level-sensitive interrupts
are not latched.
Your program can also determine whether or not interrupts can be nested.
In non-nesting mode, all interrupt requests are automatically masked out
when an interrupt service routine is entered. In nesting mode, the
processor allows higher-priority interrupts to be recognized and serviced.
There are two levels of masking for the Host Interface Port (HIP)
interrupts of the ADSP-2111, ADSP-2171, and ADSP-21msp58/59. The
memory-mapped HMASK register configures masking out the generation
of individual read or write interrupts for each HIP data register. The
IMASK register can be set to mask or enable the servicing of all HIP read
interrupts or all HIP write interrupts. Both IMASK and HMASK must be
set for HDR interrupts. See Chapter 7, “Host Interface Port,” for details.
3.4.2.1 Interrupt Control Register (ICNTL)
ICNTL is a 5-bit register that configures the external interrupt requests
(
IRQx
) of each processor. All bits in ICNTL are undefined after a
processor reset. The bit definitions for each processor’s ICNTL register are
given in Appendix E, “Control/Status Registers.”
ICNTL contains an
IRQx
sensitivity bit for each external interrupt. The
sensitivity bits determine whether a given interrupt input is edge- or level-
sensitive (0 = level-sensitive, 1 = edge-sensitive). There are no sensitivity
bits for internally generated interrupts.
The interrupt nesting enable bit (bit 4) in ICNTL determines whether
nesting of interrupt service routines is allowed.
When the value of ICNTL is changed, there is a one cycle latency before
the change in interrupt configuration.
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