Introduction 1
1 – 3
• DMA Ports—The ADSP-2181’s Internal DMA Port (IDMA) and Byte DMA
Port (BDMA) provide efficient data transfers to and from internal memory.
The IDMA port has a 16-bit multiplexed address and data bus and supports
24-bit program memory. The IDMA port is completely asynchronous and
can be written to while the ADSP-2181 is operating at full speed. The byte
memory DMA port allows boot loading and storing of program instructions
and data.
• Analog Interface—The ADSP-21msp58/59 processors include on-chip
circuitry for mixed analog and digital signal processing. This circuitry
includes an analog-to-digital converter (ADC), a digital-to-analog converter
(DAC), analog and digital filters, and a parallel interface to the processor’s
core. The converters use sigma-delta technology to capture data samples
from a highly oversampled signal.
The ADSP-2100 family architecture exhibits a high degree of parallelism,
tailored to DSP requirements. In a single cycle, any device in the family can:
• Generate the next program address.
• Fetch the next instruction.
• Perform one or two data moves.
• Update one or two data address pointers.
• Perform a computation.
In that same cycle, processors which have the relevant functional units can also:
• Receive and/or transmit data via the serial port(s).
• Receive and/or transmit data via the host interface port.
• Receive and/or transmit data via the DMA ports.
• Receive and/or transmit data via the analog interface.
1.1.2 Memory And System Interface
In each ADSP-21xx processor, four on-chip buses connect internal memory with
the other functional units: Data Memory Address bus, Data Memory Data bus,
Program Memory Address bus, and Program Memory Data bus. A single
external address bus and and a single external data bus are extended off-chip;
these buses can be used for either program or data memory access.
External devices can gain control of the processor’s buses with the bus request
and grant signals (
BR
,
BG
). The ADSP-21xx processors can continue running
while the buses are granted to another device, as long as an external memory
operation is not required.
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