9.1 OVERVIEW
This chapter describes the basic system interface features of the ADSP-2100
family processors. The system interface includes various hardware and
software features used to control the DSP processor.
Processor control pins include a
RESET signal, clock signals, flag inputs and
outputs, and interrupt requests. This chapter describes only the logical
relationships of control signals; consult individual processor data sheets for
actual timing specifications.
9.2 CLOCK SIGNALS
The ADSP-2100 family processors may be operated with a TTL-compatible
clock signal input to the CLKIN pin or with a crystal connected between the
CLKIN and XTAL pins. If an external clock is used, XTAL must be left
unconnected. The CLKIN signal may not be halted or changed in frequency
during operation.
The ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2111 processors operate
with an input clock frequency equal to the instruction cycle rate. The
ADSP-2171, ADSP-2181, and ADSP-21msp58/59 processors operate with an
input clock frequency equal to half the instruction rate; for example, a
16.67 MHz input clock produces a 33 MHz instruction rate (30 ns cycle time).
Device timing is relative to the internal clock rate which is indicated by the
CLKOUT signal.
Because these processors include an on-chip oscillator circuit, an external
crystal can be used. The crystal should be connected between the CLKIN and
XTAL pins, with two capacitors connected as shown in Figure 9.1, which can
be found on the following page. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. The frequency value selected
for the crystal should be equal to the desired instruction rate for the processor
(for the ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2111) or half the
desired instruction rate (for the ADSP-2171, ADSP-2181, and
ADSP-21msp58/59).
9System Interface
9 – 1
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