9System Interface
9 – 19
9.7.2 Entering Powerdown
The powerdown sequence is defined as follows.
1.) Initiate the powerdown sequence by applying a high-to-low transition
to the PWD pin or by setting the powerdown force control bit
(PDFORCE) in the SPORT1 Autobuffer/Powerdown Control Register.
2.) The processor vectors to the non-maskable powerdown interrupt
vector at address 0x002C. (Note: The powerdown interrupt is never
masked. You must be careful not to cause multiple powerdown
interrupts to occur or stack overflow may result. Multiple powerdown
interrupts can occur if the
PWD input is pulsed while the processor is
already servicing the powerdown interrupt.)
3.) Any number of housekeeping instructions, starting at location 0x002C,
can be executed prior to the processor entering the powerdown mode.
Typically, this section of code is used to configure the powerdown
state, disable on-chip peripherals and clear pending interrupts.
4.) The processor now enters powerdown mode when it executes an IDLE
instruction (while
PWD is asserted). The processor may take either one
or two cycles to power down depending upon internal clock states
during the execution of the IDLE instruction. All register and memory
contents are maintained while in powerdown. Also, all active outputs
are held in whatever state they are in before going into powerdown.
If an RTI is executed before the IDLE instruction, then the processor
returns from the powerdown interrupt and the powerdown sequence is
aborted.
While the processor is in the powerdown mode, the processor is in CMOS
standby. This allows the lowest level of power consumption where most
input pins are ignored. Active inputs need to be held at CMOS levels to
achieve lowest power. More information can be found in the section
“Operation During Powerdown” later in this chapter.
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