Introduction 1
1 – 11
The EZ-LAB
®
evaluation boards are low-cost, basic hardware platforms
for running example applications.
For additional information on the development tools, refer to the
ADSP-2100 Family Development Tools Data Sheet.
1.5 ORGANIZATION OF THIS MANUAL
This manual is organized as follows.
Chapters 2, 3, and 4 describe the core architectural features shared by all
members of the ADSP-2100 family:
• Chapter 2, “Computational Units,” describes the functions and internal
organization of the arithmetic/logic unit (ALU), the multiplier/
accumulator (MAC), and the barrel shifter.
• Chapter 3, “Program Control,” describes the program sequencer,
interrupt controller and status and condition logic.
• Chapter 4, “Data Transfer,” describes the data address generators
(DAGs) and the PMD-DMD bus exchange unit.
Chapters 5, 6, 7, and 8 describe the additional functional units included in
different members of the ADSP-2100 family. (See Table 1.1 for a list of the
functions included in each device.)
• Chapter 5, “Serial Ports,” describes the serial ports, SPORT0 and
SPORT1.
• Chapter 6, “Timer,” explains the programmable interval timer.
• Chapter 7, “Host Interface Port,” describes the operation of the host
interface port, including boot loading and software reset.
• Chapter 8, “Analog Interface,” describes the operation and the internal
architecture of the ADSP-21msp58/59’s analog interface.
Chapters 9 and 10 describe the behavior of the ADSP-21xx processors
from the point of view of external memory and control logic:
• Chapter 9, “System Interface,” discusses the issue of system clocking,
and describes the processors’ control interface, the software reboot
function, and the powerdown mode.
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