5 Serial Ports
5 – 28
In the worst case that all four autobuffer transfers are required at about
the same time, interrupt latency would increase by the time it takes for all
the transfers to occur, which is affected by wait states and bus request.
5.11.1 Autobuffering Control Register
In autobuffering mode, an interrupt is generated when the modification of
a specified I register (in the DAG) by the value in the specified M register
(in the DAG) causes a modulus overflow (pointer wraparound). This
means that the end of the buffer has been detected.
The autobuffering mode is enabled separately for receiving and
transmitting by bits in the SPORT’s autobuffer control register (0x3FF3 for
SPORT0 or 0x3FEF for SPORT1), shown in Figure 5.23.
The I and M registers used for autobuffering are identified by fields in the
autobuffer control register. TIREG and TMREG are binary values that
indicate the numbers of the I and M registers, respectively, associated with
the transmit buffer. The rules governing the pairing of I and M registers
are the same as for other DAG operations: the I and M registers must be in
the same DAG, numbered either 0-3 for DAG1 or 4-7 for DAG2.
Consequently, three bits identify the I register, but only two bits are
necessary to indicate the M register because the third bit (MSB) of the M
register number must be the same as for the I register.
Likewise, RIREG and RMREG indicate the numbers of the I and M
registers, respectively, associated with the receive buffer.
The TBUF and RBUF bits enable transmit autobuffering and receive
autobuffering, respectively. These bits are cleared to zeros at reset and
after a reboot. Consequently, autobuffering in progress cannot continue
through a reboot operation; you must re-enable autobuffering after a
reboot.
5.11.2 Autobuffering Example
The code shown below is an example that sets up SPORT1 for
autobuffering operation. The code assumes that the processor is driven
with a clock frequency of 12.288 MHz. The SPORT will automatically
transmit values from the circular buffer named tx_buffer. It will receive
values as they are sent to the SPORT and automatically transfer the data
into the buffer named rx_buffer. A transmit interrupt will be generated
once all of the tx_buffer values have been transferred to TX1, but before the
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