11DMA Ports
11 – 1
11.1 OVERVIEW
The ADSP-2181 supports several DMA interfacing features:
• Byte Memory & Byte Memory DMA (BDMA): this memory space can
address up to 4M bytes. The byte memory interface supports booting
from and runtime access to inexpensive 8-bit memories. The BDMA
feature lets you define the number of memory locations the ADSP-2181
will transfer to/from internal memory in the background while
continuing foreground processing.
• Internal Direct Memory Access (IDMA) Port: this parallel port
supports booting from and runtime access to host systems (for example,
PC Bus Interface ASICs). The DMA feature of this port lets you transfer
data to/from internal memory in the background while continuing
foreground processing.
These DMA transfers are accomplished internally by “cycle stealing,” in
the same way as serial port autobuffering. This means that the ADSP-2181
uses internal bus cycles to transfer the data to and from memory. The
stolen cycles will only occur at instruction cycle boundaries, i.e. not
between cycles of a multiple-cycle instruction. See “
IACK
Acknowledge &
DMA Cycle Stealing” at the end of this chapter for additional details.
The ADSP-2181 uses a half-instruction-rate clock input from which it
generates a full-instruction-rate internal clock. For example, from a 16.67
MHz clock input (CLKIN) the ADSP-2181 generates a 33.33 MHz
instruction rate clock. All timing diagrams for the processor use the full-
instruction-rate output clock (CLKOUT) as a reference.
Figure 11.1 shows an ADSP-2181 system and the interfaces to byte
memory space and the IDMA port.
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