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General| Category | Digital Signal Processor (DSP) |
|---|---|
| Word Length | 16 bits |
| Instruction Word Width | 24 bits |
| Data Bus Width | 16 bits |
| Address Bus Width | 24 bits |
| Accumulator Size | 40 bits |
| Operating Voltage | 5 V |
| Manufacturing Process | CMOS |
| Architecture | Harvard Architecture |
| Clock Speed | 10 MHz |
| On-Chip RAM | 512 words |
| Package | PQFP |
| Multiplier Size | 16x16-bit |
| I/O Ports | 8-bit parallel I/O port |
Introduction to the ADSP-2100 family architecture, DSP optimization, and manual scope.
Describes the core components: ALU, MAC, Shifter, DAGs, Program Sequencer.
Introduces the three computational units: ALU, MAC, and Barrel Shifter, and number formats.
Details the ALU's standard arithmetic and logic functions.
Covers MAC's high-speed multiplication, accumulation, and saturation functions.
Describes the shifter's functions: arithmetic, logical shifts, normalization, exponent derivation.
Describes the program sequencer, interrupt controller, and status/condition logic.
Explains how the sequencer generates instruction addresses and controls program flow.
Explains how the program sequencer responds to interrupts by vectoring to appropriate addresses.
Details registers used for interrupt configuration: ICNTL, IMASK, IFC.
Describes status registers (ASTAT, SSTAT, MSTAT) and the status stack.
Describes processor units controlling data movement and bus exchange.
Explains the two independent DAGs for indirect addressing and automatic address modification.
Describes synchronous serial ports (SPORTS) for serial data communications and interconnections.
Describes programming SPORT configuration registers and data section.
Explains how to accomplish SPORT configuration by setting bit and field values in registers.
Details autobuffering mechanism for receiving/transmitting entire data blocks.
Introduces the programmable interval timer for generating periodic interrupts.
Details timer registers TCOUNT, TPERIOD, TSCALE, and mode control.
Introduces HIP as a parallel I/O port for using processors as memory-mapped peripherals.
Details HIP's three functional blocks: HCI, data registers (HDRs), and status registers (HSRs).
Explains how the ADSP-21xx core and host computer interact via HDRs.
Covers HIP interrupts, their masking via IMASK/HMASK, and vector locations.
Explains loading internal program RAM using a boot sequence via HIP.
Introduces the analog signal interface with ADC, DAC, filters, and registers.
Details the A/D conversion circuitry including input multiplexer, PGA, and ADC.
Describes the ADC components: sigma-delta modulator, decimation filter, and digital high pass filter.
Covers the D/A conversion circuitry including DAC, smoothing filter, PGA, and output amplifier.
Details the DAC's digital filters, sigma-delta modulator, and transmit data register.
Describes operating the analog interface using memory-mapped control and data registers.
Details the analog control register and analog autobuffer/powerdown register.
Explains the analog control register for configuring ADC/DAC settings.
Shows recommended input circuit with low-pass filter and PGA.
Describes basic system interface features, hardware, and software for DSP processors.
Explains operation with TTL-compatible clock input or external crystal.
Explains the RESET signal's function for halting execution and performing a hardware reset.
Covers prioritized, individually maskable external interrupts (level- or edge-triggered).
Describes the powerdown feature for entering a low-power dormant state.
Explains control parameters for powerdown operation via SPORT1 Autobuffer/Powerdown Control Register.
Details the sequence for initiating and entering powerdown mode using PWD pin or PDFORCE bit.
Explains methods for exiting powerdown using PWD pin or RESET, and specifying start-up modes.
Describes the modified Harvard architecture, on-chip memory, and boot memory space.
Details the program memory interface for all ADSP-21xx processors except ADSP-2181.
Describes the data memory interface for all ADSP-21xx processors except ADSP-2181.
Describes the boot memory interface for loading internal program memory from external sources.
Describes bus request and grant feature for relinquishing bus control to external devices.
Details ADSP-2181 specific memory features like overlay, I/O, byte memory, and IDMA.
Explains ADSP-2181 program memory addressing and overlay capabilities.
Details ADSP-2181 data memory addressing, overlays, and wait states.
Introduces ADSP-2181 DMA interfacing features: BDMA and IDMA.
Covers BDMA port's 8-bit wide byte memory space for program code or data.
Explains how BDMA port loads/stores program instructions and data from/to byte memory.
Details memory-mapped registers for setup and control of BDMA transfers.
Covers loading on-chip program memory from external source using byte memory booting.
Describes IDMA port as a parallel I/O port for accessing internal memory by host systems.
Explains how IDMA port lets host systems access internal memory locations.
Covers booting through the IDMA port using specific reset and pin settings.
Introduces ADSP-21xx processors from a programming standpoint: units, registers, peripherals.
Details DAG registers (I, M, L) for pointers, modification, and circular buffers.
Covers registers controlling subroutines, loops, interrupts, and mode selection.
Details ICNTL, IFC, and IMASK registers for interrupt control.
Describes stack status (SSTAT), arithmetic status (ASTAT), and mode status (MSTAT) registers.
Describes registers for ALU, MAC, and Shifter units.
Covers SPORT registers for control, companding, and autobuffering.
Describes HIP registers: data, status, and interrupt mask registers.
Lists memory-mapped registers for the analog interface (ADC, DAC, control).
Shows a simple way to download programs from a host via memory interface using bus request/grant.
Details interfacing a codec with ADSP-21xx serial ports for analog-to-digital conversion.
Explains sending DSP process output analog information directly to a DAC via serial port.
Describes receiving analog signals into digital samples via serial port from an ADC.
Outlines the development process using tools like System Builder, Assembler, Linker, Simulators.
Explains FIR transversal filter structure obtained from discrete-time convolution equation.
Describes the FFT program with subroutines for scrambling, FFT computation, and scaling.
Provides a complete reference organized by instruction group and individual instruction.
Gives an overview and detailed reference for the ADSP-2100 family instruction set.
Illustrates the power of multifunction instructions combining data moves and computations.
Explains the sum-of-products operation common in DSP algorithms.
Groups instructions for computations in ALU, MAC, and Shifter units.
Explains how MOVE instructions move data to and from registers and memory.
Covers instructions like JUMP, CALL, DO UNTIL, and IDLE for controlling program flow.
Gives a summary of the complete instruction set, defining opcode field names.
Describes the non-restoring divide algorithm, operands, and cycle counts.
Introduces 16-bit fixed-point data support and block floating-point format.
Enables fixed-point processor to gain dynamic range of floating-point without overhead.
Lists interrupts and associated vector addresses for each ADSP-2100 family processor.
