9System Interface
9 – 13
FO (SPORT1 only) Flag Out value undefined unchanged
CLKODIS CLKOUT disable 0 unchanged
BIASRND MAC biased rounding 0 unchanged
Host Interface Port Registers (memory-mapped)
HDR0-5 HIP data registers undefined used during HIP reboot
HSR6 HIP status register 0x0000 used during HIP reboot
HSR7 HIP status register 0x0080 unchanged
HMASK HIP interrupt enables 0 unchanged
Analog Autobuffer/Powerdown Registers
ARBUF Receive autobuffer enable 0 0
ATBUF Transmit autobuffer enable 0 0
control bits Analog autobuffer control bits 0 unchanged
Table 9.7 ADSP-21msp58/59 State After Reset Or Software Reboot
9.4.1 ADSP-2181 Register Values for BDMA Booting
The state of some ADSP-2181 registers during reset and rebooting is
influenced by the MMAP and BMODE pins. If these pins are set for a BDMA
boot, the values in the BDMA registers change as shown in Table 9.8.
Register Process Description* Value Before Boot Value After Boot
BIAD BDMA Internal Memory Address. 0 0x20
Set for internal address 0.
BEAD BDMA External Memory Address. 0 0x60
Set for external address 0.
BTYPE BDMA Transfer Word Type. 0 0
Set for 24-bit program memory words.
BDIR BDMA Transfer Direction. 0 0
Set to transfer data from byte memory.
BMPAGE BDMA Page Selection. 0 0
Set to byte memory page 0.
BWCOUNT BDMA Word Count. 0x20 0
Set to transfer 32 words.
BMWAIT BDMA Port Wait States. 0x7 0x7
Set to 7 waits per transfer.
BCR BDMA Context Reset. ** 1 1
Table 9.8 BDMA Registers Before And After Initial Boot Loading
* Assuming MMAP=0 and BMODE=0 for a BDMA boot.
** Set to 1 to (a) holdoff instruction execution during BDMA transfer,
(b) start execution at address PM(0x0000) after BDMA transfer, and
(c) leave a BDMA interrupt pending. This sequence of events occurs if
BCR is set before BWCOUNT is written, or after the initial boot.
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