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Syntax: reg = <data> ;
dreg = <data> ;
data: <constant>
‘%’ <symbol>
‘^’ <symbol>
Permissible registers
dregs (Instruction Type 6) regs (Instruction Type 7)
(16-bit load)(maximum 14-bit load)
AX0 MX0 SI SB CNTR
AX1 MX1 SE PX OWRCNTR (write only)
AY0 MY0 SR1 ASTAT RX0
AY1 MY1 SR0 MSTAT RX1
AR MR2 IMASK TX0
MR1 ICNTL TX1
MR0 I0-I7 IFC(write only )
M0-M7
L0-L7
Example: I0 = ^data_buffer;
L0=%data_buffer;
Description: Move the data value specified to the destination location.
The data may be a constant, or any symbol referenced with the “length of”
(%) or “pointer to” (^) operators. The data value is contained in the
instruction word, with 16 bits for data register loads and up to 14 bits for
other register loads. The value is always right-justified in the destination
location after the load (bit 0 maps to bit 0). When a value of length less than
the length of the destination is moved, it is sign-extended to the left to fill
the destination width.
Note that whenever MR1 is loaded with data, it is sign-extended into MR2.
For this instruction only, the RX and TX registers may be loaded with a
maximum of 14 bits of data (although the registers themselves are 16 bits
wide). To load these registers with 16-bit data, use the register-to-register
move instruction or the data memory-to-register move instruction with
direct addressing.
Status Generated: None affected.
MOVE
LOAD REGISTER IMMEDIATE
(instruction continues on next page)
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