13 Hardware Examples
13 – 12
13.6 SERIAL PORT TO SERIAL PORT INTERFACE
The serial ports provide a convenient way to transfer data between ADSP-
21xx processors without using external memory or the memory bus and
without halting either processor. The serial ports are connected as shown
in Figure 13.9—in this example, SPORT1 of processor #1 is connected to
SPORT0 of processor #2.
The serial clock used by both processors is generated internally by
processor #1. Processor #2 is configured to receive its serial clock
externally. The serial port control registers should be set up with the
following parameters.
Processor 1, SPORT1 Processor 2, SPORT0
SCLKDIV = system-dependent SCLKDIV = system-dependent
SLEN = system-dependent SLEN = system-dependent
ISCLK = 1 ISCLK = 0
TFSR = 1 TFSR = 1
RFSR = 1 RFSR = 1
IRFS = 0 IRFS = 0
ITFS = 1 ITFS = 1
RFSDIV = don’t care RFSDIV = don’t care
TFSW1 = RFSW1 = TFSW2 = RFSW2 = system-dependent
INVRFS1 = INVTFS1 = INVRFS2 = INVTFS2 = system-dependent
Figure 13.9 Serial Port Interface Between Two ADSP-21xx Processors
ADSP-21xx
#1
RFS1
TFS1
DT1
DR1
SCLK1
SPORT1 ADSP-21xx
#2
RFS0
TFS0
DT0
DR0
SCLK0
SPORT0
Frame synchronization is used to coordinate the transfer of serial data.
Each processor generates a transmit frame sync (TFS) signal internally and
expects to receive its receive frame sync (RFS) signal externally, from the
other processor. The framing mode can be normal or alternate, but must
be the same for both SPORTs. Likewise, the SPORTs must be configured
for the same serial word length and companding type, if companding is
used, or data format if companding is not used.
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