Analog Devices adsp-2100 User Manual

11DMA Ports
11 – 21
IRD
IAD15-0
PREVIOUS
DATA
IS
IACK
Figure 11.11 IDMA Short Read Cycle Timing
11.3.4.4 Long Write Cycle
The host writes the contents of an internal memory location using the
IDMA long write cycle. The write cycle, shown in Figure 11.12, consists of
the following steps:
1. Host ensures that
IACK line is low.
2. Host asserts
IWR and IS (low), directing the ADSP-2181 to write the
data on the IAD15-0 address/data bus to the location pointed to by the
target IDMA address .
3. ADSP-2181 deasserts the
IACK line, indicating it recognizes the IDMA
write operation.
4. Host drives the data on the IAD address/data bus.
5. ADSP-2181 asserts
IACK line, indicating it latched the data on the
IAD15-0 address/data bus.
6. Host recognizes the
IACK line is now low, stops driving the data on
the IDMA address/data bus and deasserts
IWR and IS (ending the
IDMA Long Write Cycle).
Note that IAL is low (inactive) and IRD is high (inactive) throughout the
write operation.

Analog Devices adsp-2100 Specifications

General

Brand	Analog Devices
Model	adsp-2100
Category	Computer Hardware
Language	English