11 DMA Ports
11 – 22
IACK
IS
IAD15-0 DATA
IWR
Figure 11.12 IDMA Long Write Cycle Timing
Note: IDMA port writes to Program Memory require two IDMA port
write cycles to write a word to ADSP-2181 internal Program Memory. The
ADSP-2181 acknowledges the IDMA port write of the first 16 bits (MSBs
of PM word) as they are written to a temporary holding latch, not waiting
for an instruction cycle boundary. The ADSP-2181 does not assert the
IACK
line after the second Program Memory write (or all Data Memory
writes) until the internal memory write is complete and the IDMA port is
ready for another transaction.
Warning: Host IDMA write accesses to internal Program Memory take
two IDMA port writes (24-bit word through a 16-bit port). If an IDMA
address latch cycle or a ADSP-2181 write to the IDMA Control register
occurs after a first program memory write cycle, the IDMA port “loses”
the Program Memory word without changing the contents of ADSP-2181
internal memory. The next IDMA read or write uses the address selected
by the new contents of the IDMA Control register.
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