COBHAM GR740 User Manual

GR740-UM-DS, Nov 2017, Version 1.7 219 www.cobham.com/gaisler
GR740
• Two FIFOs with a depth of eight words each
• Two 128 MiB PCI BARs marked as prefetchable. One 8 MiB PCI BAR marked as non-prefetch-
able. The sizes given here are default sizes. The BAR sizes are configurable (down to a minimum
size of 8 MiB) and the BARs can also be disabled.
• Device interrupt generation
• PCI interrupt sampling and forwarding
15.2.2 PCI Configuration Space
The core implements the following registers in the PCI Configuration Space Header. For more
detailed information regarding each field in these registers please refer to the PCI Local Bus Specifi-
cation.
Table 248.GRPCI2: Implemented registers in the PCI Configuration Space Header
PCI address offset Register
0x00 Device ID, Vendor ID
0x04 Status, Command
0x08 Class Code, Revision ID
0x0C BIST, Header Type, Latency Timer, Cache Line Size
0x10 - 0x24 Base Address Registers
0x34 Capabilities Pointer
0x3C Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line
Table 249.0x00 - Device ID and Vendor ID register
31 16 16 15 0
Device ID Vendor ID
0x0061 0x1AC8
rr
31: 16 Device ID, 0x0740
15: 0 Vendor ID, 0x1AC8

COBHAM GR740 Specifications

General

Brand	COBHAM
Model	GR740
Category	Computer Hardware
Language	English