GR740-UM-DS, Nov 2017, Version 1.7 255 www.cobham.com/gaisler
GR740
Table 308. 0x04 - IRQE - GR1553B IRQ Enable Register
31 1817161511109873210
RESERVED BMTOE BMDE RESERVED RTTEE RTDE RTEVE RESERVED BCWKE BCDE BCEVE
0 00 0 000 0 000
r rw rw r rw rw rw r rw rw rw
31: 18 RESERVED
17 BM Timer overflow interrupt enable (BMTOE)
16 BM DMA error interrupt enable (BMDE)
15: 11 RESERVED
10 RT Table access error interrupt enable (RTTEE)
9 RT DMA error interrupt enable (RTDE)
8 RT Transfer-triggered event interrupt enable (RTEVE)
7: 3 RESERVED
2 BC Wake up timer interrupt enable (BCWKE)
1 BC DMA Error Enable (BCDE)
0 BC Transfer-triggered event interrupt enable (BCEVE)
Table 309. 0x10 - HC - GR1553B Hardware Configuration Register
31 30 12 11 10 9 8 7 0
MOD RESERVED XKEYS ENDIAN SCLK CCFREQ
0 0 000 0
r r rrr r
31 Modified (MOD) - Reserved to indicate that the core has been modified / customized in an unspecified man-
ner
30: 12 RESERVED
11 Safety Key (XKEYS) - Set if safety keys are enabled for the BM Control Register and for all RT Control Reg-
ister fields.
10 : 9 AHB Endianness (ENDIAN) - 00=Big-endian, 01=Little-endian, 10/11=Reserved
8 Same clock (SCLK) - Reserved for future versions to indicate that the core has been modified to run with a
single clock
7 : 0 Codec clock frequency (CCFREQ) - Reserved for future versions of the core to indicate that the core runs at
a different codec clock frequency. Frequency value in MHz, a value of 0 means 20 MHz.
Table 310. 0x40 - BCSC - GR1553B BC Status and Config Register
313028271716151110987320
BCSUP BCFEAT RESERVED BCCHK ASADL - ASST SCADL SCST
1 0b101 0 0 0 0 0 0 0
rrrrwrrrrr
31 BC Supported (BCSUP) - Reads ‘1’ if core supports BC mode
30: 28 BC Features (BCFEAT) - Bit field describing supported optional features (‘1’=supported):
30
29
28
BC Schedule timer supported
BC Schedule time wake-up interrupt supported
BC per-RT bus swap register and STBUS descriptor bit supported
27: 17 RESERVED
16 Check broadcasts (BCCHK) - Writable bit, if set to ‘1’ enables waiting and checking for (unexpected)
responses to all broadcasts.
15: 11 Asynchronous list address low bits (ASADL) - Bit 8-4 of currently executing (if ASST=01) or next asynchro-
nous command descriptor address
10 RESERVED
9: 8 Asynchronous list state (ASST) - 00=Stopped, 01=Executing command, 10=Waiting for time slot
7: 3 Schedule address low bits (SCADL) - Bit 8-4 of currently executing (if SCST=001) or next schedule descrip-
tor address
2: 0 Schedule state (SCST) - 000=Stopped, 001=Executing command, 010=Waiting for time slot, 011=Sus-
pended, 100=Waiting for external trigger