GR740-UM-DS, Nov 2017, Version 1.7 307 www.cobham.com/gaisler
GR740
21.3.1 Interrupt level register
Table 379.0x000 - ILEVEL - Interrupt level register
0x10C Interrupt acknowledge timestamp 0 register
0x110 Interrupt timestamp counter register
0x114 Interrupt timestamp 1 control register
0x118 Interrupt assertion timestamp 1 register
0x11C Interrupt acknowledge timestamp 1 register
0x120 - 0x1FC Reserved
0x200 Processor 0 reset start address register (silicon revision 0)ï€
Processor 0 boot address register (silicon revision 1)
0x204 Processor 1 reset start address register (silicon revision 0)ï€
Processor 1 boot address register (silicon revision 1)
0x208 Processor 2 reset start address register (silicon revision 0)ï€
Processor 2 boot address register (silicon revision 1)
0x20C Processor 3 reset start address register (silicon revision 0)ï€
Processor 3 boot address register (silicon revision 1)
0x210 - 0x23C Reserved
0x240 Processor boot register (silicon revision 0)ï€
Reserved (silicon revision 1)
0x300 Interrupt map register 0
0x304 Interrupt map register 1
0x308 Interrupt map register 2
0x30C Interrupt map register 3
0x310 Interrupt map register 4
0x314 Interrupt map register 5
0x318 Interrupt map register 6
0x31C Interrupt map register 7
31 16 15 1 0
RESERVED IL[15:1] R
0NR0
rrw0
31:16 Reserved
15:1 Interrupt Level n (IL[n]) - Interrupt level for interrupt n
0 Reserved
Table 378.Interrupt Controller registers
APB address offset Register