GR740-UM-DS, Nov 2017, Version 1.7 31 www.cobham.com/gaisler
GR740
MEM_DQ[81] (as pin name) IO (none) I PCI_AD[17] IO
MEM_DQ[80] (as pin name) IO (none) I PCI_AD[16] IO
MEM_DQ[63] (as pin name) IO ETH1_RXD[7] I PCI_AD[15] IO
MEM_DQ[62] (as pin name) IO ETH1_RXD[6] I PCI_AD[14] IO
MEM_DQ[61] (as pin name) IO ETH1_RXD[5] I PCI_AD[13] IO
MEM_DQ[60] (as pin name) IO ETH1_RXD[4] I PCI_AD[12] IO
MEM_DQ[59] (as pin name) IO ETH1_RXD[3] I PCI_AD[11] IO
MEM_DQ[58] (as pin name) IO ETH1_RXD[2] I PCI_AD[10] IO
MEM_DQ[57] (as pin name) IO ETH1_RXD[1] I PCI_AD[9] IO
MEM_DQ[56] (as pin name) IO ETH1_RXD[0] I PCI_AD[8] IO
MEM_DQ[55] (as pin name) IO ETH1_RXDV I PCI_AD[7] IO
MEM_DQ[54] (as pin name) IO ETH1_RXER I PCI_AD[6] IO
MEM_DQ[53] (as pin name) IO ETH1_COL I PCI_AD[5] IO
MEM_DQ[52] (as pin name) IO ETH1_CRS PCI_AD[4] IO
MEM_DQ[51] (as pin name) IO ETH1_MDINT PCI_AD[3] IO
MEM_DQ[50] (as pin name) IO (none) I PCI_AD[2] IO
MEM_DQ[49] (as pin name) IO (none) I PCI_AD[1] IO
MEM_DQ[48] (as pin name) IO (none) I PCI_AD[0] IO
MEM_DQ[47] (as pin name) IO (none) I PCI_CBE[3] IO
MEM_DQ[46] (as pin name) IO (none) I PCI_CBE[2] IO
MEM_DQ[45] (as pin name) IO (none) I PCI_CBE[1] IO
MEM_DQ[44] (as pin name) IO (none) I PCI_CBE[0] IO
MEM_DQ[43] (as pin name) IO (none) I PCI_FRAME IO
MEM_DQ[42] (as pin name) IO (none) I PCI_REQ O
MEM_DQ[41] (as pin name) IO (none) I PCI_GNT I
MEM_DQ[40] (as pin name) IO (none) I PCI_IRDY IO
MEM_DQ[39] (as pin name) IO (none) I PCI_TRDY IO
MEM_DQ[38] (as pin name) IO (none) I PCI_PAR IO
MEM_DQ[37] (as pin name) IO (none) I PCI_PERR IO
MEM_DQ[36] (as pin name) IO (none) I PCI_SERR IO
MEM_DQ[35] (as pin name) IO (none) I PCI_DEVSEL IO
MEM_DQ[34] (as pin name) IO (none) I PCI_STOP IO
MEM_DQ[33] (as pin name) IO (none) I PCI_INTA IO
MEM_DQ[32] (as pin name) IO (none) I PCI_INTB I
MEM_DQM[11] (as pin name) O ETH1_GTXCLK I PCI_M66EN I
MEM_DQM[10] (as pin name) O ETH1_TXCLK I PCI_HOSTN I
MEM_DQM[7] (as pin name) O ETH1_RXCLK I PCI_IDSEL I
MEM_DQM[6] (as pin name) O (none) I PCI_CLK I
MEM_DQM[5] (as pin name) O (none) I PCI_INTC I
MEM_DQM[4] (as pin name) O (none) I PCI_INTD I
* See section 40.3 for pin assignments
Table 27. Multiplexed SDRAM interface pins with PCI or Ethernet interfaces
Pin name*
SDRAM function
(MEM_IFWIDTH=LOW)
ETHERNET1 function
(MEM_IFWIDTH=HIGH,
PCIMODE_ENABLE=LOW)
PCI function
(MEM_IFWIDTH=HIGH,
PCIMODE_ENABLE=HIGH)
Signal Dir Signal Dir Signal Dir
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