COBHAM GR740 - Page 340

GR740-UM-DS, Nov 2017, Version 1.7 340 www.cobham.com/gaisler
GR740
25.3.1 Unlock register
Table 431.0x00 - UNLOCK - Unlock register
25.3.2 Clock enable register
Table 432.0x04 - CLKEN - Clock enable register
25.3.3 Core reset register
Table 433. 0x08 - RESET - Reset register
31 11 10 0
RESERVED UNLOCK
00
rrw
31: 11 RESERVED
10: 0 Unlock clock enable and reset registers (UNLOCK) - The bits in clock enable and core reset regis-
ters can only be written when the corresponding bit in this field is 1.
31 11 10 0
RESERVED ENABLE
0*
rrw
31: 11 RESERVED
10: 0 Cock enable (ENABLE) - A ‘1’ in a bit location will enable the corresponding clock, while a ‘0’ will
disable the clock.
The reset value of this register is set by bootstrap signals. See table 429 and section 4.9.
31 11 10 0
RESERVED RESET
0*
rrw
31: 11 RESERVED
10: 0 Reset (RESET) - A reset will be generated as long as the corresponding bit is set to ‘1’.
The reset value of this register is set by bootstrap signals. See table 429 and section 4.9.