GR740-UM-DS, Nov 2017, Version 1.7 348 www.cobham.com/gaisler
GR740
26.3.3 Counter max/latch registers
Table 439.0x100-0x13C - CSVAL0-15 - Counter 0-15 max/latch register
26.3.4 Timestamp register
Table 440.0x180 - TSTAMP - Timestamp register
31 0
CSVAL
NR
rw*
31: 0 Counter max/latch value (CSVAL) - This register holds the current value of the counter max/latch
register.
If the counter control register field CD is ‘1’, then the value displayed by this register will be the
maximum counter value reached with the settings in the counter’s control register.
If the counter control register field CDis ‘0’, then the value displayed by this register is the latched
(saved) counter value. The counter value is saved whenever a write access is made to the core in
address range 0x100 - 0x1FC (all counters are saved simultaneously). If the counter control register
CL field is set, then the current counter value will be cleared when the counter value is saved into
this register.
31 0
TSTAMP
NR
rw*
31: 0 Timestamp (TSTAMP) - Timestamp saved at latch of counters. The timestamp value uses the DSU
timer as time source. The same timer is available as the processor’s internal up-counter, for interrupt
timestamping and in the time-tag of the trace buffers. The time value is saved whenever a write
access is made to the core in address range 0x100 - 0x1FC.
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