GR740-UM-DS, Nov 2017, Version 1.7 347 www.cobham.com/gaisler
GR740
26.3.2 Counter control registers
Table 438.0x80-0xCC - CCTRL0-15 - Counter 0-15 control register
31 28 27 23 22 21 20 19 18 17 16 15 14 13 12 11 4 3 0
NCPU NCNT MC IA DS EE AE EL CD SU CL EN EVENT ID CPU/AHBM
0x3 0xF 1 1 1 1 1 NR NR NR NR 0 NR NR
r r r r r r r rw rw rw rw rw rw rw
31: 28 Number of CPU (NCPU) - Number of supported processors - 1
27: 23 Number of counters (NCNT) - Number of implemented counters - 1
22 Maximum count (MC) - If this field is ‘1’ then this counter has support for keeping the maximum
count value.
21 Internal AHB count (IA) - If this field is ‘1’ the core supports events 0x17 and 0x18
20 DSU support (DS) - If this field is ‘1’ the core supports events 0x40-0x5F
19 External events (EE) - If this field is ‘1’ the core supports external events (events 0x60 - 0x6F)
18 AHBTRACE Events (AE) - If this field is ‘1’ the core supports events 0x70 - 0x7F.
17 Event Level (EL) - The value of this field determines the level where the counter keeps running
when the CD field below has been set to ‘1’. If this field is ‘0’ the counter will count the time
between event assertions. If this field is ‘1’ the counter will count the cycles where the event is
asserted. This field can only be set if the MC field of this register is ‘1’.
16 Count maximum duration (CD) - If this bit is set to ‘1’ the core will save the maximum time the
selected event has been at the level specified by the EL field. This also means that the counter will be
reset when the event is activated or deactivated depending on the value of the EL field.
When this bit is set to ‘1’, the value shown in the counter value register will be the maximum current
value which may be different from the current value of the counter.
This field can only be set if the MC field of this register is ‘1’.
15: 14 Supervisor/User mode filter (SU) - “01” - Only count supervisor mode events, “10” - Only count
user mode events, others values - Count events regardless of user or supervisor mode. This setting
only applies to events 0x0 - 0x3A.
When SU = “1x” only events generated by the CPU/AHB master specified in the CPU/AHBM field
will be counted. This applies to events 0x40 - 0x7F
13 Clear counter on read (CL) - If this bit is set the counter will be cleared when the counter’s value is
read. The register holding the maximum value will also be cleared, if implemented.
If an event occurs in the same cycle as the counter is cleared by a read then the event will not be
counted. The counter latch register can be used to guarantee that no events are lost
12 Enable counter (EN) - Enable counter
11: 4 Event ID to be counted
3: 0 CPU or AHB master to monitor.(CPU/AHBM) - The value of this field does not matter when select-
ing one of the events coming from the Debug Support Unit or one of the external events.
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