GR740-UM-DS, Nov 2017, Version 1.7 75 www.cobham.com/gaisler
GR740
6.10.7 I-cache and D-cache configuration registers
The configuration of the two caches if defined in two registers: the instruction and data configuration
registers. These registers are read-only, except for the REPL field that can be written, and indicate the
size and configuration of the caches. They are located under ASI 2 at offset 8 and 12.
Table 56. ASI 0x2, 0x08 and 0x09C - CCFG - Cache configration registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CL R REPL SN WAYS WSIZE LR LSIZE RESERVED M RESERVED
0 0 1 0b011 0x2 0 0b100 0x000 1 0b000
rrrwrr r rr r rr
31 Cache locking (CL) - Set if cache locking is implemented (always zeo).
30 RESERVED
29: 28 Cache replacement policy (REPL) - 00 - no replacement policy (direct-mapped cache), 01 - least
recently used (LRU), 10 - least recently replaced (LRR), 11 - random.
This field is writable, default (reset) value is "01" = LRU.
27 Cache snooping (SN) - Value 1 to signify that snooping is supported.
26: 24 Cache associativity (WAYS) - "011" - 4-way associative.
23: 20 Way size (WSIZE) - Indicates the size (KiB) of each cache way. This field has value 2. Size =
2
SIZE
=4 KiB way size.
19 Local ram (LR) - 0 in this implementation to signify that local RAMis not implemented.
18: 16
Line size (LSIZE) - Indicated the size (words) of each cache line. Set to 2. Line size = 2
LSIZE
= 4
words = 32 bytes.
15: 4 RESERVED
3 MMU present (M) - This bit is set to ‘1’ to signify that an MMU is present.
2: 0 RESERVED
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