GR740-UM-DS, Nov 2017, Version 1.7 76 www.cobham.com/gaisler
GR740
6.10.8 MMU control register
The MMU control register is located in ASI 0x19 offset 0.
Table 57. ASI 0x19, 0x00- MMUCTRL - MMU control register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMPL VER ITLB DTLB R TD ST RESERVED P
S
O
RESERVED NF E
0x0 0x0 0b100 0b100 0 NR 1 0 0 0 0 0
r r r r r rw r r rw r rw rw
31: 28 MMU Implementation ID (IMPL) - Hardcoded to “0000”
27: 24 MMU Version ID (VER) - Hardcoded to “0000”.
23: 21
Number of ITLB entries (ITLB) - The number of ITLB entries is calculated as 2
ITLB
= 2
4
= 16.
20: 18
Number of DTLB entries (DTLB) - The number of DTLB entries is calculated as 2
DTLB
= 2
4
= 16.
17: 16 RESERVED
15 TLB disable (TD) - When set to 1, the TLB will be disabled and each data access will generate an
MMU page table walk. The TLB should not be disabled on GR740 silicon revision 0, see section
43.2.9.
14 Separate TLB (ST) - This bit is set to 1 to signify that separate instruction and data TLBs are imple-
mented
13: 8 RESERVED
7 Partial Store Ordering (PSO) - This field is writable but does not have an effect on processor opera-
tion.
6: 2 RESERVED
1 No Fault (NF) - When NF= 0, any fault detected by the MMU causes FSR and FAR to be updated
and causes a fault to be generated to the processor. When NF= 1, a fault on an access to ASI 9 is han-
dled as when NF= 0; a fault on an access to any other ASI causes FSR and FAR to be updated but no
fault is generated to the processor.
0 Enable MMU (E) - 0 = MMU disabled, 1 = MMU enabled.
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