4-72 120 Series Maternal/Fetal Monitor Revision B
2015590-001
Theory of Operation: MSpO2 Board
RCAL resistor in the sensor which connects between pin 6 of JP1 and ground to
become part of a voltage divider with R16. Power for this divider is a 2.5 V
reference on the Nellcor module. This calibration voltage (VCAL2) is
communicated to the DAC via buffer U21B.
Input Amplifier and Synchronous Detector
The SAT signal is conditioned by the input amplifier and the synchronous detector
to provide signal gain and reduce or eliminate the effects of ambient interference.
Negative peak detector U7 is employed to monitor the SAT signal while it is still
DC-coupled; it produces a DC output proportional to the maximum negative
excursion of the SAT signal pulses. If the negative excursions of the SAT signal
exceed –10 V, the modules’s microprocessor, that is monitoring the output of U7A
(COMPARE1), initiates action to reduce the output of the dual DAC that controls
LED intensity. The microprocessor may reduce current through only one of the
LEDs if necessary.
The SAT signal is then coupled through C55 to remove the DC offset or steady-state
ambient energy artifact. The signal is then coupled to band-pass filter U13B to
remove noise. The output of U13B is then introduced to a programmable gain
circuit consisting of DAC U9 and operational amplifier U13A.
The signal is then coupled to full-gain amplifier U14B. The output of U14B is used
by the modules’s microprocessor as the sense point to determine input channel gain
requirements. Positive peak detector U7B is employed to monitor the amplified
SAT signal at the output of U14B. It produces a DC output (COMPARE2)
proportional to the positive excursion of the amplified SAT signal pulses. If
(COMPARE2) exceeds +10 V, the modules’s microprocessor reduces U13A gain.
The microprocessor may also reduce LED drive for one LED if necessary.
The SAT signal is finally coupled to the synchronous detector comprised of U10B,
U14A, and associated resistors. When the positive input of U14A is grounded by
U10B, the device is an inverting amplifier with a gain of one. When this input is not
grounded, the device becomes a voltage follower with a gain of one. The output of
the synchronous detector is applied to the filter/amplifier circuitry.
Filters/Amplifiers
The module includes two separate active filter channels: infrared and red. These
low-pass filter/amplifier circuits and associated gating circuits recover the patient’s
pulse waveform from the multiplexed SAT signal. FET switches U15A and U15B
are employed to separate the infrared information in the SAT signal from the red
information. The gate control input signals (IRGATE/ and REDGATE/) are
processor-controlled and operate in time sequence with the four-phase LED drive
control. This switching action is used to control the inputs to the red and infrared
filter / amplifier circuits.
The infrared filter/amplifier circuit is an active low-pass filter (total gain = 4) which
responds to the patient’s pulse modulation — reproducing the patient’s pulse
waveform at the filter/amplifier output. The infrared pulses (IR) are coupled to the
first of two identical filter/amplifier stages (U22D and U22B), each having a gain of
approximately two. The signal is then coupled to the last stage (U23B) which has a
gain of one. The pulse waveform (IR) at the output of the filter/amplifier stages,
must always be at a positive voltage level in order to be digitized by the analog-to-
digital conversion circuitry. The final amplifier stage has an input offset of +25 mV
to ensure that the waveform does not move to a negative level. The output (IR
ADC) is then coupled to the analog-to-digital conversion section.
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