4-12 120 Series Maternal/Fetal Monitor Revision B
2015590-001
Theory of Operation: Main Motherboard
Table 4-6. NBP Board Connector J4
Pin Number Signal Name Signal type Signal Description
1 GND Output +5 V Power Ground Return
2 D0B I/O Buffered Data Line
3 D2B I/O Buffered Data Line
4 D4B I/O Buffered Data Line
5 D6B I/O Buffered Data Line
6 D8B I/O Buffered Data Line
7 D10B I/O Buffered Data Line
8 +5V Output Volt Logic Supply
9 D12B I/O Buffered Data Line
10 D14B I/O Buffered Data Line
11 A1B Output Buffered Address Line
12 A3B Output Buffered Address Line
13 A5B Output Buffered Address Line
14 A7B Output Buffered Address Line
15 GND Output +5 Volt Power Ground Return
16 A9B Output Buffered Address Line
17 A11B Output Buffered Address Line
18 A13B Output Buffered Address Line
19 A15B Output Buffered Address Line
20 SP2B/ Output Spare Chip Select Line
21 SP4B/ Output Spare Chip Select Line
22 +5V Output +5 Volt Logic Supply
23 UDSB/ Output Buffered Upper Data Strobe
24 +15BP Output +15 Volt Supply for NBP Module
25 +12VEL Output +12 Volt Analog Supply
26 GNDBP Output NBP Module Ground
27 GNDBP Output NBP Module Ground
28 IACK6/ Output Processor Interrupt Acknowledge Line
29 IRQ6/ Input Processor Interrupt Line
30 GND Output Digital Ground
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