13: BIT SHIFT / ROTATE INSTRUCTIONS
13-4 OPENNET CONTROLLER USER’S MANUAL
Examples: SFTR
• Data Type: Word
• Data Type: Double Word
M8120
REP
M8120 is the initialize pulse special internal relay.
When the CPU starts operation, the MOV (move) instruction sets 29 to
data register D10.
Each time input I0 is turned on, 16-bit data of data register D10 is
shifted to the right by 2 bits as designated by operand bits. The last bit
status shifted out is set to a carry (special internal relay M8003). Zeros
are set to the MSB.
SOTU
I0
S1 –
29
D1 –
D10
S1
D10
bits
2
SFTR(W)
MOV(W)
0Before shift: D20 = 29 0 0 0000 0 0 0 0 0110 1 1
CY
M8003
MSB LSB
D10
0After first shift: D20 = 7 10 0000 0 0 0 0 1000 0 1
CY
M8003
MSB LSB
D10
Bits to shift = 2
0
10 0000 0 0 0 0 0000 0 0After second shift: D20 = 1
CY
M8003
MSB LSB
D10
1
0
0
Shift to the right
Each time input I1 is turned on, 32-bit data of data registers D10 and
D11 is shifted to the right by 2 bits as designated by operand bits.
The last bit status shifted out is set to a carry (special internal relay
M8003). Zeros are set to the MSBs.
Bits to shift = 2
SOTU
I1
S1
D10
bits
2
SFTR(D)
0
Before shift: D10·D11 = 1,900,573
0 0 0000 0 0 0 0 0110 1 1
CY
M8003
MSB LSB
D10·D11
0
After shift: D10·D11 = 475,143
11 0000 0 0 0 0 1000 0 1
CY
M8003
MSB LSB
D10·D11
Shift to the right
10 0000 0 0 0 0 1000 0 1
0 0 0000 0 0 0 0 0110 1 1
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