Intel 386

ix
CONTENTS
12.2.4 Bus Control Arbitration ............................................................................................12-9
12.2.5 Ending DMA Transfers ..........................................................................................12-10
12.2.6 Buffer-transfer Modes ...........................................................................................12-12
12.2.6.1 Single Buffer-Transfer Mode ............................................................................12-12
12.2.6.2 Autoinitialize Buffer-Transfer Mode ..................................................................12-12
12.2.6.3 Chaining Buffer-Transfer Mode ........................................................................12-12
12.2.7 Data-transfer Modes .............................................................................................12-13
12.2.7.1 Single Data-transfer Mode ...............................................................................12-14
12.2.7.2 Block Data-transfer Mode ................................................................................12-18
12.2.7.3 Demand Data-transfer Mode ............................................................................12-21
12.2.8 Cascade Mode ......................................................................................................12-25
12.2.9 DMA Interrupts ......................................................................................................12-26
12.2.10 8237A Compatibility ..............................................................................................12-27
12.3 REGISTER DEFINITIONS......................................................................................... 12-28
12.3.1 Pin Configuration Register (PINCFG) ...................................................................12-31
12.3.2 DMA Configuration Register (DMACFG) ..............................................................12-32
12.3.3 Channel Registers ................................................................................................12-33
12.3.4 Overflow Enable Register (DMAOVFE) ................................................................12-34
12.3.5 Command 1 Register (DMACMD1) .......................................................................12-35
12.3.6 Status Register (DMASTS) ...................................................................................12-36
12.3.7 Command 2 Register (DMACMD2) .......................................................................12-37
12.3.8 Mode 1 Register (DMAMOD1) ..............................................................................12-38
12.3.9 Mode 2 Register (DMAMOD2) ..............................................................................12-40
12.3.10 Software Request Register (DMASRR) ................................................................12-42
12.3.11 Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK) .........12-44
12.3.12 Bus Size Register (DMABSR) ...............................................................................12-46
12.3.13 Chaining Register (DMACHR) ..............................................................................12-47
12.3.14 Interrupt Enable Register (DMAIEN) .....................................................................12-48
12.3.15 Interrupt Status Register (DMAIS) ........................................................................12-49
12.3.16 Software Commands ............................................................................................12-50
12.4 DESIGN CONSIDERATIONS.................................................................................... 12-50
12.5 PROGRAMMING CONSIDERATIONS...................................................................... 12-50
12.5.1 DMA Controller Code Examples ...........................................................................12-51
CHAPTER 13
SYNCHRONOUS SERIAL I/O UNIT
13.1 OVERVIEW ................................................................................................................. 13-1
13.1.1 SSIO Signals ...........................................................................................................13-4
13.2 SSIO OPERATION...................................................................................................... 13-5
13.2.1 Baud-rate Generator ...............................................................................................13-5
13.2.2 Transmitter ..............................................................................................................13-6
13.2.2.1 Transmit Mode using Enable Bit ........................................................................13-7
13.2.2.2 Autotransmit Mode ...........................................................................................13-12
13.2.2.3 Slave Mode ......................................................................................................13-12