4-1
CHAPTER 4
SYSTEM REGISTER ORGANIZATION
This chapter provides an overview of the system registers incorporated in the Intel386™ EX pro-
cessor, focusing on register organization from an address architecture viewpoint. The chapters
that cover the individual peripherals describe the registers in detail.
This chapter is organized as follows:
• Overview (see below)
• I/O Address Space for PC/AT Systems (page 4-2)
• Expanded I/O Address Space (page 4-3)
• Organization of Peripheral Registers (page 4-5)
• I/O Address Decoding Techniques (page 4-6)
• Addressing Modes (page 4-9)
• Peripheral Register Addresses (page 4-15)
4.1 OVERVIEW
The Intel386 EX processor has register resources in the following categories:
• Intel386 processor core architecture registers:
— General purpose registers
— Segment registers
— Instruction pointer and flags
— Control registers
— System address registers (protected mode)
— Debug registers
— Test registers
• Intel386 EX processor peripheral registers:
— Configuration space control registers
— Interrupt control unit registers
— Timer/counter unit registers
— DMA unit registers (8237A-compatible and enhanced function registers)
— Asynchronous serial I/O (SIO) registers
— Clock generation selector registers
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