Intel 386

18-13
JTAG TEST-LOGIC UNIT
Figure 18-6. Internal and External Timing for Loading a Data Register
A2362-01
Run - Test / Idle
Select - DR - Scan
Capture - DR
Shift - DR
Exit1 - DR
Pause - DR
Exit2 - DR
Shift - DR
Exit1 - DR
Update - DR
Run - Test / Idle
TDI
Data Input to IR
IR Shift-Register
Parallel Output of IR
Data Input to TDR
TDR Shift-Register
Parallel Output of TDR
Instruction Register
TDO Enable
TDO
= Don't care or undefined.
IDCode
Instruction
New Data
Test Data Register
Inactive
Active
Inactive
Active
Inactive
Select - DR - Scan
Select - IR - Scan
Test - Logic - Reset
Old Data
Controller State
TMS
TCK